Hardware Accelerators for Low Power Digital Signal Processing
- Manuel De La Guia
Main Research Topic
- Design and development of custom Low Power DSP blocks for mobile and biomedical applications.
- Integration of Low Power structures within EEDSP algorithms.
- Application, development and evaluation of fault-tolerant architectures for power reduction.
Areas of Study
- Low Power Techniques: A wide range of techniques that allow the reduction of power in CMOS technology has be reviewed. From the implementation side including multi Vdd, multi-Vt and Power Scaling to the design stage where pipelining and reduced multipliers, plenty of choices have been studied and some of them applied to achieve the lowest power consumption with an optimal functionality.
- Tree-based Multipliers: Multipliers play a key role in the overall power figures of any DSP system. Tree-based structures such as Wallace or Dadda have been considered, implemented and simulated to check their benefits against other full-parallel implementations such as matrix architectures.
- Low Power DSP Architectures: When designing fixed-point DSP blocks resolution is usually tied to power consumption. Some techniques such as Wordlength Reduction and Truncated Multipliers can be of use in situations where some degradation in the output data is acceptable. Figure 1 shows an example of power reductions achieved by such techniques when applied to a 16-bit multiplier.
- Fixed Point Arithmetic.
- Design on Verilog: Verilog is an efficient way of describing digital circuitry. It allows reusability and is easy to debug. It can also produce accurate simulations in short amounts of time.
- ASIC design Flow: One of our goals in UL is to produce a working demonstrator in silicon that allows one or some of our architectures to physically and interact with some other parts of the EEDSP project, so the whole design flow has been studied by attending to two Cadence tools courses, with the aim of reproducing it in our Lab.
- Conference paper accepted in ISSC09 with the title “Data Wordlength Reduction in 90nm Multipliers”.
- EEDSP workshop presentation in June 2009 with the title “Power reduction using truncated multipliers”,
- Conference paper submitted to ISCAS2010 on Low Power Techniques.
- Provisional Layouts generated for custom DSP blocks on 90nm technology. (Figure 2)
- Study the effect of Reduced Architectures in more complex DSP architectures. Analyze power benefits and limitations regarding usability.
- Explore the potential of Fault Tolerant techniques when applied to ultra-low power DSP blocks.
- Complete Design Flow in Cadence.
- Identified some potential for collaboration with the Galway branch of EEDSP.