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Publications 2006

A. Byrne and W. P. Marnane. Versatile processor for GF(pm) arithmetic in cryptographic applications. In 24th IEEE Norchip Conference, pages 281--284, November 2006.

R. McEvoy, J. Curran, P. Cotter, and C. Murphy. Fortuna: Cryptographically secure pseudo-random number generation in software and hardware. In IET Irish Signals and Systems Conference --- ISSC 2006, pages 457--462. IET, June 2006.

R. McEvoy and C. Murphy. Efficient all-or-nothing encryption using CTR mode. In International Conference on Security and Cryptography - SECRYPT 2006, pages 237--245. INSTICC Press, 2006.

M. Keller, T. Kerins, F. Crowe, and W. P. Marnane. FPGA implementation of a GF(2m) tate pairing architecture. In K. Bertels, J. M. P. Cardoso, and S. Vassiliadis, editors, International Workshop on Applied Reconfigurable Computing --- ARC 2006, volume 3985 of Lecture Notes in Computer Science, pages 358--369. Springer-Verlag, 2006.

T. Kerins, E. M. Popovici, W. P. Marnane, and P. S. L. M. Baretto. An FPGA implementation of a flexible secure elliptic curve cryptography processor. International Journal of Electronics, 93(6):349--372, June 2006.

M. Keller, R. Ronan, W. P. Marnane, and C. Murphy. A GF(24m) inverter and its application in a reconfigurable tate pairing processor. In IEEE 3rd International Conference on ReConFigurable Computing and FPGAs 2006 --- ReConFig ’06, pages 158--167. IEEE, September 2006.

W. Marnane and F. Crowe. Hardware complexity of cryptographic algorithms. In Special Session on Coding and Cryptography at Fourth Irish Conference on the Mathematical Foundations of Computer Science and Information Technology '06 --- MFCSIT '06, pages 275--278, 2006.

R. P. McEvoy, F. M. Crowe, C. C. Murphy, and W. P. Marnane. Optimisation of the SHA-2 family of hash functions on FPGAs. In IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures. IEEE, 2006.

M. C. Pérez, J. Urena, A. Hernández, W. P. Marnane, and C. De Marziani. Implementación hardware de un correlador eficiente de macrosecuencias generadas a partir de conjuntos complementarios de secuencias. In VI Workshop on Reconfigurable Computing and Applications --- JCRA 2006, pages 167--172, September 2006.

M. C. Pérez, J. Urena, A. Hernández, C. De Marziani, A. Ochoa, and W. P. Marnane. FPGA implementation of an efficient correlator for complementary sets f sequences. In IEEE 2006 International Conference on Programmable Logic and Applications, pages 697--700. IEEE, August 2006.

R. Ronan, C. O'hEigeartaigh, T. Kerins, W. P. Marnane, M. Scott, and C. Murphy. An embedded processor for a pairing-based cryptosystem. In Third International Conference on Information Technology : New Generations --- ITNG '06, pages 192--197. IEEE, 2006.

R. Ronan, C. O'hEigeartaigh, C. Murphy, M. Scott, and T. Kerins. FPGA acceleration of the tate pairing in characteristic 2. In IEEE International Conference on Field Programmable Technology, pages 213--220. IEEE, 2006.

Publications 2004

R. Bresnan, W. P. Marnane, and M. Sala. Efficient low-density parity-check decoding. In IEE Irish Signals and Systems Conference 2004, pages 613--618. IEE, June--July 2004.

F. Crowe, A. Daly, T. Kerins, and W. P. Marnane. Single-chip FPGA implementation of a cryptographic co-processor. In IEEE International Conference on Field-Programmable Technology, pages 279--285. IEEE, 2004.

F. Crowe, A. Daly, T. Kerins, and W. P. Marnane. Design of an efficient interface between an FPGA and external memory. In IEE Irish Signals and Systems Conference 2004, pages 118--123. IEE, June-July 2004.

A. Daly, W. P. Marnane, T. Kerins, and E. M. Popovici. An FPGA implementation of GF(p) ALU for encryption processors. Elsevier Journal on Microprocessors and Microsystems, Special Issue on FPGAs: Applications, Algorithms and Tools, 28(5--6):253--260, May-June 2004.

A. Daly, W. P. Marnane, T. Kerins, and E. M. Popovici. New Algorithms, Architectures and Applications for Reconfigurable Computing, chapter 18: Divison in GF(p) for Application in Elliptic Curve Cryptosystems on Field Programmable Logic, pages 219--229. Springer-Verlag, 2004.

T. Kerins, W. P. Marnane, and E. Popovici. Design for reuse elliptic curve cryptosystem processors for FPGAs. In IEE Irish Signals and Systems Conference 2004, pages 577--582. IEE, June-July 2004.

T. Kerins, E.M. Popovici, and W.P. Marnane. Fully paramaterisable galois field arithmetic processor over GF(3m) suitable for elliptic curve cryptography. In IEEE 24th International Conference on Microelectronics, volume 2, pages 739--742. IEEE, 2004.

T. Kerins, E. M. Popovici, and W. P. Marnane. Algorithms and architectures for use in FPGA implementations of identity based encryption schemes. In J. Becker, M. Platzner, and S. Vernalde, editors, Field-Programmable Logic and Applications --- FPL 2004, volume 3203 of Lecture Notes in Computer Science, pages 74--83. Springer-Verlag, 2004.

C. M. Lucey and C. C. Murphy. Generalising wavelet-based error correction coding via polyphase constraints. In WSEAS International Conference on Wavelet Analysis & Multirate Systems - WAMUS 2004. WSEAS, 2004.

G. Murphy, E. M. Popovici, R Bresnan, W. P. Marnane, and P. Fitzpatrick. Design and implementation of a parameterizable LDPC decoder IP core. In IEEE 24th International Conference on Microelectronics, volume 2, pages 747--750. IEEE, May 2004.

Publications 2005

F. Crowe, A. Daly, T. Kerins, and W. P. Marnane. New Trends of Embedded Cryptographic Systems, chapter 1: A Scalable Dual Mode Arithmetic Unit for Public Key Cryptosystems, pages 5-22. Nova Science Publishers, 2005.

F. Crowe, A. Daly, and W. P. Marnane. A scalable dual mode arithmetic unit for public key cryptosystems. In IEEE International Conference on Information Technology: Coding and Computing --- ITCC '05, volume 1, pages 568-573. IEEE, 2005.

F. Crowe, A. Daly, and W. P. Marnane. Optimised montgomery domain inversion on FPGA. In European Conference on Circuit Theory and Design --- ECCTD 2005, 2005.

F. Crowe, T. Kerins, A. Daly, E. M. Popovici, and W. P. Marnane. Industry Days 2003-2004, chapter 6: Prototyping of Cryptographic Algorithms, pages 49--56. Società Editrice Esculapio, 2005.

M. Keller, T. Kerins, and W. P. Marnane. FPGA implementation of a GF(24m) multiplier for use in a pairing based cryptosystem. In IEEE 2005 International Conference on Programmable Logic and Applications, pages 594--597. IEEE, 2005.

T. Kerins, W. P. Marnane, E. M. Popovici, and P. S. L. M. Barreto. Efficient hardware for the tate pairing calculation in characteristic three. In J. R. Rao and B. Sunar, editors, Cryptographic Hardware and Embedded Systems --- CHES 2005, volume 3659 of Lecture Notes in Computer Science, pages 412--426. Springer-Verlag, 2005.

T. Kerins, W. P. Marnane, E. M. Popovici, and P. S. L. M. Baretto. Hardware accelerators for pairing based cryptosystems. IEE Proceedings on Information Security, Special Issue on Cryptographic Algorithms and Architectures for System on Chip, 152(1):47--56, October 2005.

T. Kerins, E. M. Popovici, and W. P. Marnane. An FPGA implementation of a flexible secure elliptic curve cryptography processor. In J. M. P. Cardoso, editor, International Workshop on Applied Reconfigurable Computing --- ARC 2005, volume 1, pages 22--30. IADIS, 2005.

C. M. Lucey and C. C. Murphy. On the structure of 2-channel paraunitary finite field multirate filter banks. In International Conference on Circuit Theory and Design, pages 357-360, 2005.

C. Spagnol, E. M. Popovici, and W. P. Marnane. Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder. In European Conference on Circuit Theory and Design --- ECCTD 2005, August 2005.

C. Spagnol, E. M. Popovici, and W. P. Marnane. New algorithm for LDPC decoding over GF(q). In IEE Irish Signals and Systems Conference 2005, pages 425--430. IEE, September 2005.

Publications 2007

A. Byrne, N. Meloni, F. Crowe, W. P. Marnane, A. Tisserand, and E. M. Popovici. SPA resistant elliptic curve cryptosystem using addition chains. In Information Technology 2007 --- ITNG '07, pages 995--1000. IEEE, 2007.

M. Joye and M. Tunstall. Securing OpenSSL against micro-architectural attacks. In J. Hernando, E. Fernández-Medina, and M. Malek, editors, International Conference on Security and Cryptography --- SECRYPT 2007, pages 189--196. INSTICC Press, 2007.

M. Keller and W. Marnane. Hardware architectures for the tate pairing over GF(2m). Computer & Electrical Engineering, Special Issue on Security of Computer and Networks, 33(5-6):392--406, 2007.

T. Kerins, E. M. Popovici, and W. P. Marnane. Versatile hardware architectures for GF(pm) arithmetic in public key cryptography. Integration the VLSI Journal: Embedded Cryptographic Hardware, 40(1):28--35, January 2007.

M. Keller and W. Marnane. Low power elliptic curve cryptography. In N. Azémard and L. J. Svensson, editors, International Workshop on Power and Timing Modeling, Optimization and Simulation --- PATMOS 2007, volume 4644 of Lecture Notes in Computer Science, pages 310-319. Springer-Verlag, 2007.

C. M. Lucey and C. C. Murphy. Constraint based design of 2-channel paraunitary filter banks of a given length over GF(2r). IEEE Transactions on Signal Processing, 55(5):1940-1944, 2007.

R. P. McEvoy, M. Tunstall, C. C. Murphy, and W. P. Marnane. Differential power analysis of HMAC based on SHA-2, and countermeasures. In S. Kim, M. Yung, and H.-W. Lee, editors, Workshop on Information Security Applications --- WISA 2007, volume 4867 of Lecture Notes in Computer Science, pages 317-332. Springer-Verlag, 2007.

R. P. McEvoy, M. Tunstall, C. Whelan, N. Hanley, C. C. Murphy and W. P. Marnane, Differential Power Analysis of the HMAC Algorithm, Presented at the Rump Session of Cryptographic Hardware and Embedded Systems --- CHES 2007.

W. P. Marnane, Hardware Complexity of Cryptographic Algorithms, Elliptic Curve Cryptography --- ECC 2007, Dublin 2007.

K. Nguyen and M. Tunstall. Montgomery multiplication with redundancy check. In L. Breveglieri, S. Gueron, I. Koren, D. Naccache, and J.-P. Seifert, editors, Fault Diagnosis and Tolerance in Cryptography 2007 --- FDTC 07, pages 30--36. IEEE, 2007.

R. Ronan, C. O'hEigeartaigh, C. Murphy, M. Scott, and T. Kerins. Hardware acceleration of the tate pairing on a genus 2 hyperelliptic curve. Elsevier Journal of Systems Architecture, Special Issue on Embedded Hardware for Cryptosystems, 53(2--3), February/March 2007.

R. Ronan, C. O'hEigeartaigh, C. Murphy, T. Kerins, and P. S. L. M. Barretto. A reconfigurable processor for the cryptographic h T pairing in characteristic 3. In Information Technology 2007 --- ITNG '07, pages 11--16. IEEE, 2007.

M. Tunstall and O. Benoit. Efficient use of random delays in embedded software. In D. Sauveron, K. Markantonakis, A. Bilas, and J.-J. Quisquater, editors, Information Security Theory and Practices 2007 --- Smart Cards, Mobile and Ubiquitous Computing Systems --- WISTP 2007, volume 4462 of Lecture Notes in Computer Science, pages 27--38. Springer-Verlag, 2007.

M. Tunstall, N. Hanley, R. P. McEvoy, C. Whelan, C. C. Murphy, and W. P. Marnane. Correlation power analysis of large word sizes. In IET Irish Signals and System Conference --- ISSC 2007, pages 145--150. IET, 2007.

Publications 2003

F. Crowe, A. Daly, T. Kerins, and W. P. Marnane. A reconfigurable TLS protocol processor. In Irish Signals and Systems Conference 2003, pages 256--361, June 2003.

F. Crowe and W. P. Marnane. Hardware acceleration of cryptographic ciphers used in the transport layer security (TLS) protocol. In Irish Telecommunications Systems Research Symposium 2003, May 2003.

A. Daly, W. P. Marnane, T. Kerins, and E.M. Popovici. Fast modular divison for application in ECC on reconfigurable logic. In P. Y. K. Cheung, G. A. Constantinides, and J. T. de Sousa, editors, Field-Programmable Logic and Applications --- FPL 2003, volume 2778 of Lecture Notes in Computer Science, pages 786-795. Springer--Verlag, 2003.

A. Daly, W. P. Marnane, and E. Popovici. Fast modular inversion in the montgomery domain on reconfigurable logic. In Irish Signals and Systems Conference 2003, pages 362--367, June 2003.

C. McIvor, M. McLoone, J. McCanny, A. Daly, and W. Marnane. Fast montgomery modular multiplication and RSA cryptographic processor architectures. In 37th Asilomar Conference on Signals, Systems, and Computers, volume 1, pages 379--384. IEEE, 2003.

G. Murphy, E. Popovici, and W. P. Marnane. Design trade-off for the implementation of LDPC encoders. In Irish Signals and Systems Conference 2003, pages 506--511, June 2003.

D. K. Singh, W. P. Marnane, and P. Fitzpatrick. Reconfigurability of turbo codes for differentiatied QOS. In Irish Signals and Systems Conference 2003, pages 542--547, June 2003.

Publications 2002

A. Daly and W. P. Marnane. Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic. In Tenth International Symposium on Field Programmable Gate Arrays, pages 40--49. ACM Press, February 2002.

T. Kerins, E. Popovici, A. Daly, and W. P. Marnane. Hardware encryption engines for e-commerce. In Irish Signals and Systems Conference 2002, pages 89--94, June 2002.

T. Kerins, E. M. Popovici amd W. P. Marnane, and P. Fitzpatrick. Fully parameterisable elliptic curve cryptography processor over GF(2m). In M. Glesner, P. Zipf, and M. Renovell, editors, Field-Programmable Logic and Applications --- FPL 2002, volume 2438 of Lecture Notes in Computer Science, pages 750--759. Springer-Verlag, 2002.

W. P. Marnane, G. Lightbody, and D. Pesch, editors. Proceedings of Irish Signals and Systems Conference 2002. 2002.

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