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Hardware Wrapper

We present a hardware wrapper interface which attempts to encompass all the competition entries (and indeed, hash algorithms in general) across any number of both FPGA and ASIC hardware platforms. This interface comprises communications and padding, and attempts to standardise the hashing algorithms to allow accurate and fair area, timing and power measurement between the different designs.

Our wrapper design is currently on version 2.


MES = Message length
DIG = Digest length
CTW = Counter width
MBL = Maximum block length
SR = Shift register
  • Counter Unit
  • Needed for all except : Keccak, Luffa, CubeHash, Shabal
  • Groestl counts blocks, not message length
  • Padder
Slight variations between each hash function.

Core components :
  • Multiplexer to select the type of padding (100...., 000...., CTR, etc) for the current 32-bit block
  • 32, 32-bit shift registers (1 for each shift value)
  • A multiplexer with the outputs of the 32 SRs as input. Choice is made based on the message length "mod 32"
  • Controller
Varies significantly based on the hash function
  • Typical FSM:
    • Read data in
    • Padding state
    • Load to HF
    • Read next block
    • Wait for message digest

Sub-Padding

Hamsi 384-512

Sub-Wrapper

Hamsi 384-512

Padding

Hamsi 384-512

Hardware Complexity of Cryptographic Algorithms

 

Controller

Fugue 224-256

Sub-Controller

Fugue 224-256

Hash Top Level

Fugue 224-256

Cryptography Research Group

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