Publications 2006

A. Byrne and W. P. Marnane. Versatile processor for GF(pm) arithmetic in cryptographic applications. In 24th IEEE Norchip Conference, pages 281--284, November 2006.


R. McEvoy, J. Curran, P. Cotter, and C. Murphy. Fortuna: Cryptographically secure pseudo-random number generation in software and hardware. In IET Irish Signals and Systems Conference --- ISSC 2006, pages 457--462. IET, June 2006.


R. McEvoy and C. Murphy. Efficient all-or-nothing encryption using CTR mode. In International Conference on Security and Cryptography - SECRYPT 2006, pages 237--245. INSTICC Press, 2006.


M. Keller, T. Kerins, F. Crowe, and W. P. Marnane. FPGA implementation of a GF(2m) tate pairing architecture. In K. Bertels, J. M. P. Cardoso, and S. Vassiliadis, editors, International Workshop on Applied Reconfigurable Computing --- ARC 2006, volume 3985 of Lecture Notes in Computer Science, pages 358--369. Springer-Verlag, 2006.


T. Kerins, E. M. Popovici, W. P. Marnane, and P. S. L. M. Baretto. An FPGA implementation of a flexible secure elliptic curve cryptography processor. International Journal of Electronics, 93(6):349--372, June 2006.


M. Keller, R. Ronan, W. P. Marnane, and C. Murphy. A GF(24m) inverter and its application in a reconfigurable tate pairing processor. In IEEE 3rd International Conference on ReConFigurable Computing and FPGAs 2006 --- ReConFig ’06, pages 158--167. IEEE, September 2006.


W. Marnane and F. Crowe. Hardware complexity of cryptographic algorithms. In Special Session on Coding and Cryptography at Fourth Irish Conference on the Mathematical Foundations of Computer Science and Information Technology '06 --- MFCSIT '06, pages 275--278, 2006.


R. P. McEvoy, F. M. Crowe, C. C. Murphy, and W. P. Marnane. Optimisation of the SHA-2 family of hash functions on FPGAs. In IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures. IEEE, 2006.


M. C. Pérez, J. Urena, A. Hernández, W. P. Marnane, and C. De Marziani. Implementación hardware de un correlador eficiente de macrosecuencias generadas a partir de conjuntos complementarios de secuencias. In VI Workshop on Reconfigurable Computing and Applications --- JCRA 2006, pages 167--172, September 2006.


M. C. Pérez, J. Urena, A. Hernández, C. De Marziani, A. Ochoa, and W. P. Marnane. FPGA implementation of an efficient correlator for complementary sets f sequences. In IEEE 2006 International Conference on Programmable Logic and Applications, pages 697--700. IEEE, August 2006.


R. Ronan, C. O'hEigeartaigh, T. Kerins, W. P. Marnane, M. Scott, and C. Murphy. An embedded processor for a pairing-based cryptosystem. In Third International Conference on Information Technology : New Generations --- ITNG '06, pages 192--197. IEEE, 2006.


R. Ronan, C. O'hEigeartaigh, C. Murphy, M. Scott, and T. Kerins. FPGA acceleration of the tate pairing in characteristic 2. In IEEE International Conference on Field Programmable Technology, pages 213--220. IEEE, 2006.

Cryptography Research Group