Gary Murphy graduated in 2004.
Masters Thesis Title: Design and Implementation of an Efficient Parameterisable LDPC Codec
Abstract: Low Density Parity Check codes are generally considered to be the next-generation forward error correction code. They are currently been considered for applications as diverse as hard drives and 4G phones to deep space communication. The reason for this is that the hardware required to implement a LDPC codec is an order of magnitude less complex than that of a Turbo code with a similar BER performance. Record breaking LDPC codes have been developed that have a BER performance that is within 0.0045db of the Shannon Limit.
This thesis investigates the algorithms used by Low-Density Parity Check codes and develops an efficient and parameterisable way of designing an LDPC codec. An accurate software model of the encoding and decoding algorithms for LDPC codes is developed and used to determine the ideal BER performance of any LDPC code as well as providing statistical data about the decoding process. This simulation model is extended to include the effects of hardware constraints and provide a test platform on which hardware implementations can be compared.
Two types of LDPC encoders are developed, a direct implementation of the encoding algorithm using XOR gates and a more versatile memory based encoder that is fully parameterisable in terms of bus widths and bit encoders. Various trade-o®s between area, latency and clock cycles are discussed.
A design methodology for a fully parameterisable LDPC decoder that is closely tied to the simulation software is developed. A method by which the the hardware can be completely parameterised in terms of the internal bus width of the interconnect and the Á lookup tables is shown. A proof of concept ASIC targeted towards a 4 metal layer 0.35m CMOS technology was designed and fabricated using the design methodology presented in this thesis.