Biography

Emanuel Popovici is Lecturer with the Department of Microelectronic Engineering, National University of Ireland, Cork since 2002.  He received the Dipl. Ing. degree in Computer Engineering from the Politehnica University Timisoara, Romania (1997) and a PhD in Microelectronic Engineering from the National University of Ireland (2002), respectively. Between 1997 and 2001 he did his research on efficient algorithms and architectures for encoding/decoding of block codes within the National Microelectronics Research Centre(now the Tyndall National Institute), Ireland.  Prior to his appointment as Lecturer, he was postdoctoral research engineer with University College Cork working on hardware accelerators for e-commerce cryptography. His research interests include low power embedded system design for reliable and secure computing and communications, and electronic design automation.

Keywords

Low Power Embedded Systems, Error Correcting Codes, Cryptography and Cryptanalysis, Digital ASIC Design, FPGA/FPSoC, Power Analysis (Estimation and Optimisation) for SoC/NoC, Design Automation for Low Power Wireless Sensor Networks, Reversible Circuits and Computing Architectures.

Membership

Emanuel Popovici is a Senior Member of IEEE, Member of ACM, and he is also associated with the Boole Centre for Research in Informatics(BCRI), Centre for Efficiency Oriented Languages(CEOL), Tyndall National Institute(TNI), and Claude Shannon Institute(CSI). Since 2006, Dr. Popovici is also a member of MIDAS Ireland.

Lecturing Responsibilities

Dr. Emanuel M. Popovici teaches 4 courses and coordinates other two modules. 

   Teaching:

• UE3005: Microelectronic Design Automation
• UE4004: Microelectronic System Design
• UE4009: Test and Testability  
• UE5001: HDL Synthesis

   Coordinating:

• UE4020: Final Year Project
• UE5019: Postgraduate Research Report

Research interests

The Embedded Systems research group is primarily focusing on low power design for hardware-software systems, applications of coding theory and cryptography in computing and communications applications. The research areas include: 

• Error-correcting codes for communication and computer systems(Reed-Solomon, Hermitian, LDPC),
• Cryptography(Elliptic and Hyperelliptic, AES, IDEA-NXT, Chaos),
• Design automation for low power embedded systems,
• Digital testing and design for testability,
• Protocols and design methodologies for Sensor networks,
• Low power(estimation and optimisation) SoC/NoC and FPGA design. 

He has previously graduated 2PhD, 3 Research Masters, 12 Taught Masters and 3 HDip students. Dr. Emanuel Popovici also supervised 4 Postdoctoral researchers. Currently he is supervising or co-supervising 3 Postdoctoral researchers, 8 PhDs, and 3 Taught Masters students. Research funding is provided through major SFI projects(namely SRC-EEDSP, CSET-Clarity, PI, NAP, Mathematics Initiative-CSI), Enterprise Ireland, IDA/Synopsys or  IRCSET(EMBARK).    

Embedded Systems Group

Summary of activities in the Embedded Systems group:

We study various issues related to the modelling, design and implementation of reliable and secure low power embedded systems including algorithms, architectures and applications. In particular we focus on the low power design methodology, security and reliability in the context of SoC/NoC and wireless sensor networks(WSN).

Postdoctoral Researchers:

Dr. Massimiliano Sala (BCRI, 2005-2006, now with University of Trento)

Dr. Kalok Man (CEOL, 2007-2009, now with Jiaotong-Liverpool University, China)

Dr. Christian Spagnol (EEDSP, 2008-)

Dr. Chong Shen (CLARITY, Tyndall, 2008-2009, now with University of Strathclyde)

Dr. Maziar Goudarzi (CEOL, 2009, now with Sharif University, Iran)

Dilip Vasudevan(CEOL, 2009-)

Dr. Fernando Hernando(CSI, 2009- )

Postgraduate Students:

• Gary Murphy (M.Eng.Sc./Research), graduated 2004:Design and Implementation of an Efficient parameterisable LDPC codec (FPGA and 0.35um ASIC implementations).  
• Chandrika Sahajanand (M. Eng. Sc/Taught), graduated 2004: Smart antennas: design and FPGA implementation of a digital adaptive beamformer  
• Colm O'Keeffe (M.Eng.Sc/Taught), graduated 2005: IDEA NXT implementation: a hardware-software codesign approach (reference design, wikipedia) 
• Andrew Byrne (M.Eng.Sc/Taught), graduated 2005: Versatile architectures for decoding a class of LDPC codes  
• Peadar Delaney (H. Dip./Taught), graduated 2005:   Encoding of LDPC codes
• Andrew Robson (H. Dip./Taught), graduated 2005:   MIMO communication systems
• Eva O'Reagan (H. Dip./Taught),  to graduate 2008: Process Algebras for digital circuit design. 
• Asnarani Rangasami (M.Eng.Sc/Taught), graduated 2006: Low power testing using built-in-self test architectures 
• Anthony O'Halloran (M.Eng.Sc/Taught), graduated 2006: Codes on graphs 
• James McDonagh (M.Eng.Sc/Taught), graduated 2006: LDPC codes using quasi-cyclic encoding 
• Hemanth Chintalapani (M.Eng.Sc/Taught), graduated 2006: Efficient encoding and decoding of low density parity check codes. 
• Brian Baldwin (M.Eng.Sc/Taught), graduated 2007:  Fault Insertion Side Channel Attacks Platform for Feistel Scheme Block Ciphers.
• Weibo Pan (M.Eng.Sc/Taught), graduated 2008, (co-supervision with Dr. Sverre Lidholm): Implementation and Evaluation of a Finite Field Processor ASIC
• Rachit Agarwal (M.Eng.Sc/Research), graduated 2007, (co-supervision with Brendan O'Flynn): Algebraic-Geometric Codes: Low Complexity Algorithms and VLSI Architectures. 
• Gerard Murphy (MEngSc/Research), graduated 2008: Cryptography for resource constrained embedded systems.
• Luigi Giancardi (MEngSc/Erasmus), graduated 2009: Data Compression for Wireless Sensor Networks.
• Hua Li (MEngSc/Taught), to graduate 2009: Low Power design Methodologies for SHA-3 algorithms.
• Jing Xu (MEngSc/Taught), to graduate 2009: Design and FPGA Implementation of SHA-3 algorithms.
• Tingcong Ye (MEngSc/Taught) to graduate 2009: Efficient static average power estimation for a class of digital circuits. 
• Stefano Rollo(MEngSc/Erasmus), to graduate 2010 (co-supervision with Brendan O'Flynn): S-LZW: Lempel Ziv Welch compression algorithm for Sensor Network.
• Riccardo Puppo(MEngSc/Erasmus), to graduate 2010: Real-Time Signal Processing of Accelerometer Data from Waist Mounted Wearable Sensor
• Francesco Laurenti(MEngSc/Erasmus), to graduate 2010 (co-supervision with Brendan O'Flynn): MAC protocols for WSN: F-mac and F_mac/ack
• Roberto Lan Cian Pan(MEngSc?Erasmus), to graduate 2010: Security algorithms for resource-constrained environments 

• Tim Kerins (PhD), graduated 2006, (co-supervision with Dr. Liam Marnane): Architectures for cryptography based on elliptic curves.  
• Sean Harte (PhD), to graduate 2009,  (co-supervision with Brendan O'Flynn): Hardware and Software Architectures for Miniaturised Heterogeneous Wireless Sensor Networks  
• Andrew Byrne (PhD), to graduate 2009, (co-supervision with Dr. Liam Marnane): Design Automation for Cryptographic Processors 
• Shraddha Srivastava (PhD), to graduate 2010: Berlekamp-Massey type decoding for some classes of block codes 
• Rashmi Mehrotra (PhD), to graduate 2010: Algorithms for Design Automation for Low Power
• Tom English (PhD), to graduate 2010: Low Power Networks on a Chip Design in Deep Submicron CMOS Technologies
• Richard McSweeney (PhD), to graduate 2011: Low Power Transceivers for medical applications
• Stevan Marinkovic (PhD), to graduate 2012: Reliable and Secure wireless sensor networks for medical applications
• Jiao Yan Chen (PhD), to graduate 2012: Applicability of static average case analysis via modular quantitative analysis to reversible circuits
• Nasim Zeinolabediny (PhD), to graduate 2012: Average and Worst Case in Predictable Embedded Systems Design 

Collaborators:

• Dr. Liam Marnane, Dept. of Electrical and Electronic Engineering, UCC
• Prof. Michel Schellekens, CEOL and Dept. of Computer Science, UCC
• Prof. Patrick Fitzpatrick, BCRI and Dept. of Mathematics, UCC 
• Prof. Michael O'Sullivan, Department of Mathematics and Statistics, SDSU
• Mr. Brendan O'Flynn, Tyndall National Institute, UCC

Other Academic Activities

• Between 2004-2006, Dr. Emanuel Popovici was the Departmental Internship Coordinator. Students from IIT Kanpur, IIT Delhi, IIT Bombay, IIT Madras (India) and University of Ferrara (Italy) worked on research projects of short  duration(typically 3 months).
• Since 2005 Dr. Emanuel Popovici coordinated the Young Scientist and Technologist Summer School. During these years, participants in the summer school obtained  numerous awards at the BT Young Scientist contest.
• Since 2007, Dr. Emanuel Popovici is the Erasmus coordinator with University of Genoa, Italy.

Publications

PhD Thesis:

E. M. Popovici, Algorithms and architectures for decoding Reed-Solomon and Hermitian codes, UCC, 2002. 

Journals and Conference Proceedings:

1.) E.M. Popovici, P. Fitzpatrick  “Division algorithm over GF(2m )” , IEE Electronics Letters, 34, No. 19, 1998, pp. 1843-1844.

2.) E. M. Popovici, P. Fitzpatrick, C.C. Murphy, “Reed-Solomon decoders for the read-write channel”, IEE System on a chip Colloquium (Digest), No. 439, 1998, pp. 9/1-9/5.

3.) E. M. Popovici, P. Fitzpatrick, C. C. Murphy,  “FPGA design trade-offs for solving the key equation in Reed-Solomon decoding”, FPL1999, Lecture Notes in Computer Science, Springer-Verlag, 1999, pp. 353-358.

4.) E. Popovici, P. Fitzpatrick,  “VLSI design for a generic Galois Field arithmetic processor”, Proceedings of the Irish Signals and Systems Conference, 2000, pp.322-327.

5.) E. M. Popovici, P. Fitzpatrick,  “Algorithm and Architecture for a Galois Field Multiplicative Arithmetic Processor”, Transactions On Information Theory, Vol. 49, No. 12, Dec. 2003, pp.3303-3307.

6.) E. Popovici, M. O’Sullivan, P. Fitzpatrick, R. Koetter, “Implementation of a Hermitian decoder”, IEEE ISIT 2001, pp. 311, Washington DC, USA.

7.) E. Popovici, P. Fitzpatrick, “Reed-Solomon Codecs for Optical Communications”,  IEEE International Microelectronics Conference, Proceedings, Nis, Yugoslavia, May 2002. pp.613-616.

8.) T. Kerins, E.M. Popovici, A. Daly, L. Marnane: “Hardware Encryption Engines for E-Commerce”, Irish Signals and Systems Conference, Proceedings, 2002, pp.89-94.

9.) T. Kerins, E.M. Popovici, L. Marnane, P. Fitzpatrick: “Fully Parameterisable Elliptic Curve Cryptography Processor over GF(2m)”, Lecture Notes in Computer Science, Springer-Verlag, September 2002, pp. 750-759.

10.) C. Wolf, P. Fitzpatrick, S. Foley, E. Popovici: “HFE in Java: Implementing Hidden Field Equations for Public Key Cryptography”, Irish Signals and Systems Conference, Proceedings, 2002, pp. 295-299.

11.) A. Daly, W. Marnane, E. Popovici, “Fast modular inversion in the Montgomery domain on reconfigurable logic”, Proc. of ISSC, 2003, pp. 362-367.

12.) G. Murphy, E. Popovici, W. Marnane, “Design trade-offs for implementation of LDPC encoders”, Proc. of ISSC, 2003, pp. 506-511.

13.) A. Daly, W. Marnane, T. Kerins, E. Popovici: “Fast modular division for applications in ECC on reconfigurable logic”, Lecture notes in computer Science, Springer-Verlag, September 2003, pp. 786-795.

14.) G. Murphy, E. M. Popovici, R. Bresnan, W.P. Marnane, P. Fitzpatrick, “Design and implementation of a Parameterisable LDPC decoder IP core”, Proceedings of MIEL 2004, Vol. 2, Nis, Yugoslavia, 2004, pp.747-750.

15.) T. Kerins, E. Popovici, W.P. Marnane, P. Fitzpatrick, “Fully Paramaterisable Galois Field Arithmetic Processor over GF(3^m) suitable for Elliptic Curve Cryptography”, Proceedings of MIEL 2004, Vol. 2, Nis, Yugoslavia, pp. 739-742 ,

16.) C. Saha, S. Bellis, A. Mathewson, E. Popovici, “Performance Enhancement Defect tolerance in the Cell Matrix architecture”, Proceedings of MIEL2004, Nis, Yugoslavia, Vol. 2, May 2004, pp 777-780.

17.) A. Daly, W. Marnane, T. Kerins, E. Popovici, “An FPGA Implementation of a GF(p) ALU for Encryption Processors”,  Elsevier Journal on Microprocessors and Microsystems (Special issue on FPGAs: Applications and Designs), Vol.28 No.5-6 pp.253-260, 2004

18.) Daly A., Marnane W. P., Kerins T., Popovici E.M., "Division in GF(p) for Application in Elliptic Curve Cryptosystems on Field Programmable Logic", Invited Chapter (Chapter 18) in New Algorithms, Architectures and Applications for Reconfigurable Computing, edited by W. Rosenstiel and P. Lysaght, Springer 2004, ISBN 1-4020-3127-0, pp. 219-229.

19.) Tim Kerins, E. Popovici, W. P. Marnane: Algorithms and Architectures for use in FPGA implementations of Identity Based Encryption schemes, FPL 2004, LNCS, Springer Verlag,  pp.74-83.

20.) Tim Kerins, W. P. Marnane, E. Popovici: Automated Design of Elliptic Curve Cryptosystem Processors for FPGAs, IEE Proceedings of Irish Signals and Systems Conference, 2004, pp. 577-582.

21.) T. Kerins, W.P. Marnane E.M. Popovici: Versatile Hardware Architectures for Arithmetic in GF(p^m) for use in Public Key Cryptography, Integration the VLSI Journal: Embedded Cryptographic Hardware, Vol. 40, No. 1, January 2007, pp. 28-35.

22.) Kerins T., Marnane W. P., Popovici E. M., Baretto P.S.L.M., Hardware Accelerators for Pairing based Cryptosystems ", IEE Proceedings on Information Security, Special Issue on Cryptographic Algorithms and Architectures for System on Chip, Vol. 152, No. 1, pp. 47-56, October, 2005.

23.) T. Kerins, W.P. Marnane E.M. Popovici: An FPGA Implementation of a Flexible Secure Elliptic Curve Cryptography Processor. Distinguished Paper. International Workshop on Applied Reconfigurable Computing ARC 2005, Proceedings, pp.22-30, IADIS press.

24.) T. Kerins, E. M. Popovici, W. P. Marnane, Algorithms and Architectures for a Flexible Elliptic Curve Cryptography Processor, International Journal of Electronics, Vol. 93, No. 6, June 2006, pp 349-372.

25.) T. Kerins, E. M. Popovici, W. P. Marnane, P.S.L.M. Barretto Efficient hardware for the Tate pairing calculation in characteristic three, January  2005, CHES2005, Springer Verlag, 2005, pp 412-426.

26.) C. O’Keeffe, E.M. Popovici: FOX Algorithm Implementation: a hardware design approach, Cryptology E-print archive, report 2005/157.

27.) A. Byrne, E. M. Popovici, M. E. O’Sullivan, Versatile Architectures for Decoding a Class of LDPC Codes, IEEE ECCTD2005 Proceedings, August 2005, Vol. 1 pp. 289-292.

28.) C. Spagnol, W. P. Marnane, E. M. Popovici Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder, IEEE ECCTD2005 Proceedings, August 2005, pp 613-618.

29.) F. Crowe, T. Kerins, A. Daly, E. Popovici, W.P. Marnane, “Rapid Prototyping of Cryptographic Algorithms", Invited Chapter (Chapter 6) in Industry Days 2003-2004, edited by Aquilano D., Bezzi M., Capasso V., Micheletti A., Naldi G., Nieus T., Rizzo O., Sala M., Società Editrice Esculapio, ISBN 88-7488-109-6, pp. 49-56

30.) C. O’Keeffe, R. Agarwal, E. Popovici, B. O’Flynn, “Low Power hardware and software implementation of IDEA NXT algorithm, Proc., Irish Signals and Systems Conference, ISSC, pp. 419-424, 2005.

31.) C. Spagnol, E. Popovici, W. P. Marnane, “New algorithm for LDPC decoding over GF(q) , IEE Proceedings of ISSC 2005, September 2005, pp. 425-430.

32.) R. Agarwal, E.M. Popovici, C.O’Keeffe, B.O’Flynn, S.J.Bellis, Low Power Computing for Secure and Reliable Sensor Networks, IEEE Proc., 25th International Conference on Microelectronics, MIEL, pp. 630-633, 2006.

33.) E. Popovici, Coding and Cryptography for resource constrained wireless sensor networks: a hardware-software co-design approach, invited paper in IEEE CAS, September 2006, IEEE Proceedings of CAS, pp 19-27.

34.) G. Murphy, A. Keeshan, R. Agarwal, E. Popovici, "Hardware-Software Implementation of Public-Key Cryptography for Wireless Sensor Networks", IEE Proc., Irish Signals and Systems Conference, ISSC, pp. 463-468, 2006 .

35.) R. Agarwal, E.M. Popovici, B. O’Flynn and M.E. O’Sullivan “A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput Constraints,” ,  IEEE Proc., International Symposium on Circuits and Systems, ISCAS, pp. 1405-1408, 2007.

36.) R. Agarwal, E.M. Popovici, and B. O’Flynn, “Adaptive Wireless Sensor Networks: A System Design Perspective to Adaptive Reliability,” Proc., 2nd IEEE Intl. Conf. Wireless Communication and Sensor Networks WCSN, pp. 216-225, December 2006 (Third Prize in Student Paper Contest)

37.) A. Byrne, N. Meloni, F. Crowe, W.P.Marnane, A. Tisserand  and E.M.Popovici , “SPA resistant Elliptic Curve Cryptosystem using Addition Chains”, In Information Technology 2007 --- ITNG '07, pages 995--1000. IEEE, 2007.

38.)  Michel Schellekens, Rachit Agarwal, Emanuel Popovici, Ka Lok Man, A Simplified Derivation of Timing Complexity Lower Bounds for Sorting by Comparisons, 2007, Nordic Journal of Computing, Vol. 13, No. 4, pp. 316-323, 2006.

39.) Rachit Agarwal, Emanuel M. Popovici, and Brendan O’Flynn, Efficient Error Control Coding for Wireless Sensor Networks, IEEE Proc., European Conference on Circuit Theory and Design, ECCTD, pp. 699-702, 2007.

40.) R. Agarwal, E. Popovici, R. Koetter, A Low Complexity Algorithm and Architecture for Systematic Encoding of Hermitian Codes, IEEE Proc., International Symposium on Information Theory ISIT, pp. 1336-1340, 2007.

41.) S. Harte, B. O'Flynn, R. Martiniez-Catala, E. Popovici,  Design and Implementation of a miniaturised, low power wireless sensor node, accepted at IEEE ECCTD 2007, March 2007.

42.) James McDonagh, Anthony O’Halloran, Emanuel Popovici, Vaibhav Katewa, Max Sala Efficient construction and implementation of Short LDPC Codes for Wireless Sensor Networks, IEEE ECCTD 2007, accepted.

43.) Rachit Agarwal, Emanuel Popovici, Brendan O’Flynn, Oscar De Feo, Energy Guided Choice of Error Recovery Protocols in Embedded Networked Sensor Systems, IEEE SensorComm, pp. 560-565, 2007.

44.) Michel Schellekens, Rachit Agarwal, Andrea Fedeli, Yiu Fai Lam, Menouer Boubekeur, Ka Lok Man, Emanuel Popovici, Towards Fast and Accurate Static Average-Case Performance Analysis of Embedded Systems: The MOQA Approach , IEEE EWDTS, pp. 371-376, 2007

45.) S. Harte, E.M. Popovici, B. O'Flynn, and C. O'Mathuna, "THAWS: Automated Design and Deployment of Heterogeneous Wireless Sensor Networks", WSEAS Transactions on Circuits and Systems, issue 9, vol. 7, sept 2008, pp. 829-838.

46.) Christian Spagnol, William Marnane, Emanuel Popovici, FPGA implementations of LDPC over GF(2^m) decoders, IEEE Proc. of SiPS 2007.

47.) G. D. Murphy, E. M. Popovici,  Efficient Implementation of Authenticated Key Establishment in Wireless Sensor Networks, IET Proc. of ISSC 2007, (Best Poster award)

48.) John Buckley, Brendan O’Flynn 1, Emanuel Popovici, Sean Cian O’Mathuna Design and Optimization of a Lumped-Element Balun for a Zigbee Wireless Sensor Node, IET CIICT, 2007, accepted.

49.) Andrew Byrne, William Marnane, Emanuel Popovici, “Versatile Processor for GF(pm) Arithmetic for use in Cryptographic Applications”, accepted, to appear in IET Computers & Digital Techniques, 2008.

50.) Rachit Agarwal, Ralf Koetter    and Emanuel M. Popovici,  A Low Complexity Algorithm and Architecture for Systematic Encoding of Hermitian Codes, http://arxiv.org/PS_cache/arxiv/pdf/0704/0704.0590v2.pdf

51.) A. Byrne, F. Crowe, W.P.Marnane, N. Meloni, A. Tisserand, E. M. Popovici, SPA resistant Elliptic Curve Cryptosystem using Addition Chains, International Journal of High Performance Systems Architecture, Vol. 1, No. 2, 2007, pp. 133-142.

52.) A. Byrne, N. Meloni, A. Tisserand, E.M. Popovici, and W.P. Marnane, Comparison of Simple Power Analysis Attack Resistant Algorithms for an Elliptic Curve Cryptosystem, Journal of Computers, Vol. 2, No. 10, 2007, pp. 52-62.

53.) J. Buckley, B. O'Flynn, E. Popovici, C. O'Mathuna, RF Performance Optimization of a 2.45GHz Zigbee Wireless Sensor Node, accepted,  Research Colloquium on Emerging Trends in Wireless Communications, Royal Irish Academy, 2008.

54. ) C. Spagnol, W. Marnane, E. Popovici, Hardware implementation of GF(2^m) LDPC decoders, accepted IEEE Circuits and Systems, March, 2008.

55.) Mark. Hamilton, Michael Tunstall, Emanuel Popovici, William Marnane, Side Channel Analysis of an Automotive Processor, IET ISSC, March 2008, accepted.

56.) Brian Baldwin, Emanuel Popovici, Michael Tunstall, William Marnane, Fault Injection Platform for Block Ciphers, IET ISSC, March 2008, accepted.

57.) G. D. Murphy, E. Popovici, W. P. Marnane, "Area Efficient Publick Key Cryptography in Wireless Sensor Networks", SENSORCOMM 2008, accepted.

58.) S. Harte, E. Popovici, B. O'Flynn,  THAWS: Automated Wireless Sensor Network Development And Deployment, DATICS 2008, accepted.

59.) R. Agarwal, E. Popovici, M. Sala and B. O'Flynn, Error Resilient Data Transport in Sensor Network Applications: A Generic Perspective, International Journal of Circuit Theory and Applications, 2008, accepted.

60.) S. Harte, B. O'Flynn, R. V. Martínez-Català, J. Buckley, and E. M. Popovici, "Wireless sensor node design for heterogeneous networks",  XXXII Int. Microelectronics and Packaging Poland Conf., September, Poland. 

61.) T. English, K.L. Man, E. Popovici, M.P. Schellekens, "HotSpot : Visualising Dynamic Power Consumption in RTL Designs",  6th IEEE East-West Design and Test International Symposium - IEEE/EWDTS'08, Lviv, Ukraine, October, 2008, BEST PAPER AWARD

62.) R. Mehrotra, T. English, K.L. Man, E. Popovici, M.P. Schellekens,  An Efficient Power Estimation and Optimisation Design Flow of Digital Circuits, accepted at IEEE ISOCC 2008.

63.) J. W. Jung, A. Kailas, M. A. Ingram, and E. Popovici, An Evaluation of Cooperation Transmission Considering Practical Energy Models and Passive Reception," Proc. 1st International Symposium on Applied Sciences in Bio-Medical and Communication Technologies (ISABEL), Aalborg, Denmark, Oct. 25-28, 2008.

64.) M. Schellekens, D. Early, E. Popovici, Designing software for modular static average-case analysis, to appear in IEEE Proc. of STFSSD 2009.

65.) Michel Schellekens, Diarmuid Early, Emanuel Popovici, Dilip Vasudevan,  A high level reversible language for modular average case analysis, presented at Reversible Computing 2009.

66.) Chong Shen, Brendan O'Flynn, Emanuel Popovici and Dirk Pesch, "HWN* Framework towards 4G Wireless Networks" To appear at IGI-GLOBAL, IDEA gorup, 2009.

67.) Tom English, KaLok Man, Emanuel Popovici, A Switching Activity Analysis and Visualisation  tool for Power Optimisation of SoC Buses,  IEEE PRIME 2009, accepted.

68.) Shraddha Srivastava, Christian Spagnol, Emanuel Popovici, Analysis of a Set of Error Correcting Schemes in Multi-hop Wireless Sensor Networks, IEEE PRIME 2009, accepted.

69.) S. Marinkovic, E. Popovici, C. Spagnol, S. Faul, W. Marnane, Energy-Efficient Low Duty Cycle MAC Protocol for Wireless Body Area Networks, accepted IEEE Transactions on Information Technology in BioMedicine, 2009.

70.) R. McSweeney, L. Giancardi, C. Spagnol, E. Popovici, Implementation of Source and Channel Coding for Power Reduction in Medical Application WSN, accepted at SensorComm 2009, BEST PAPER AWARD.

71.) S. Marinkovic, C. Spagnol, E. Popovici, Energy-Efficient TDMA based MAC Protocol for Wireless Body Area Networks, SensorComm 2009, BEST PAPER AWARD.

72.) C. Shen, S. Harte, E. Popovici, B. O'Flynn, Energy-aware Dynamic Route Management for THAWS, accepted at S-Cube 2009.

73.) M. Goudarzi, J. Chen, E. Popovici, M. Schellekens, 'Reversing Deterministic Finite State Machines', accepted, ISSC 2009.

74.) W. Pan, E. Popovici, S. Lidholm, L. Marnane, 'ASIC Implementation of a Finite Field Arithmetic Processor Core', accepted ISSC 2009.

75.) D. Vasudevan, M. Goudarzi, J. Chen, E. Popovici, M. Schellekens, A Reversible MIPS Multi-cycle Control FSM Design, accepted ASQED 2009.

76.) T. English, M. Keller, K. L. Man, E. Popovici, M. Schellekens, W. Marnane, A Low-power Pairing-based Cryptographic Accelerator for Embedded Security Applications, accepted at IEEE SOCC 2009.

77.) C. Shen, S. Harte, E. Popovici, B. O'Flynn, R. Atkinson, A. Ruzzelli, Automated Protocol Selection for Energy Efficient WSN Applications, Vol. 15, Issue 21, Oct. 2009, pp. 1098-1099. 

78.) S. Marinkovic, E. Popovici, Network Coding for Efficient Error Recovery in Wireless Sensor Networks for Medical Applications, accepted EMERGING 2009.

79.) T. English, K.L. Man, E. Popovici,  BSAA - a Switching Activity Analysis and Visualisation tool for SoC Power Optimisation, accepted PATMOS 2009.

80.) R. Mehrotra, K. L. Man, E. Popovici, M. Schellekens, Data structure manipulation for NNIG and PTNNIG: towards a unified power and timing analysis, accepted at IEEE SCS 2009, July 2009. 

81.) C. Spagnol, E. Popovici, Bit Flipping type algorithms for decoding LDPC over GF(2^m), submitted to IEEE Trans on Communications, August 2009.

82.) R. McSweeney, C. Spagnol, E. Popovici,  Comparative study of Software vs. Hardware Implementations of  Shortened Reed-Solomon Code for Wireless Body Area Networks, accepted at IEEE MIEL 2009.

83.) R. Mehrotra, E. Popovici, K.L. Man, M. Schellekens, Power reduction and technology mapping of digital circuits using AND Inverter Graphs, accepted at IEEE MIEL 2009.

84.) S. Marinkovic, R. Puppo, R. L. Cian Pan, E. Popovici, Implementation of a secure fall detection system for Body Area Networks, accepted at IEEE MIEL 2009.