F. Crowe, A. Daly, T. Kerins, and W. P. Marnane. New Trends of Embedded Cryptographic Systems, chapter 1: A Scalable Dual Mode Arithmetic Unit for Public Key Cryptosystems, pages 5-22. Nova Science Publishers, 2005.

 

F. Crowe, A. Daly, and W. P. Marnane. A scalable dual mode arithmetic unit for public key cryptosystems. In IEEE International Conference on Information Technology: Coding and Computing --- ITCC '05, volume 1, pages 568-573. IEEE, 2005.

 

F. Crowe, A. Daly, and W. P. Marnane. Optimised montgomery domain inversion on FPGA. In European Conference on Circuit Theory and Design --- ECCTD 2005, 2005.

 

F. Crowe, T. Kerins, A. Daly, E. M. Popovici, and W. P. Marnane. Industry Days 2003-2004, chapter 6: Prototyping of Cryptographic Algorithms, pages 49--56. Società Editrice Esculapio, 2005.

 

M. Keller, T. Kerins, and W. P. Marnane. FPGA implementation of a GF(24m) multiplier for use in a pairing based cryptosystem. In IEEE 2005 International Conference on Programmable Logic and Applications, pages 594--597. IEEE, 2005.

 

T. Kerins, W. P. Marnane, E. M. Popovici, and P. S. L. M. Barreto. Efficient hardware for the tate pairing calculation in characteristic three. In J. R. Rao and B. Sunar, editors, Cryptographic Hardware and Embedded Systems --- CHES 2005, volume 3659 of Lecture Notes in Computer Science, pages 412--426. Springer-Verlag, 2005.

 

T. Kerins, W. P. Marnane, E. M. Popovici, and P. S. L. M. Baretto. Hardware accelerators for pairing based cryptosystems. IEE Proceedings on Information Security, Special Issue on Cryptographic Algorithms and Architectures for System on Chip, 152(1):47--56, October 2005.

 

T. Kerins, E. M. Popovici, and W. P. Marnane. An FPGA implementation of a flexible secure elliptic curve cryptography processor. In J. M. P. Cardoso, editor, International Workshop on Applied Reconfigurable Computing --- ARC 2005, volume 1, pages 22--30. IADIS, 2005.

 

C. M. Lucey and C. C. Murphy. On the structure of 2-channel paraunitary finite field multirate filter banks. In International Conference on Circuit Theory and Design, pages 357-360, 2005.

 

C. Spagnol, E. M. Popovici, and W. P. Marnane. Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder. In European Conference on Circuit Theory and Design --- ECCTD 2005, August 2005.

 

C. Spagnol, E. M. Popovici, and W. P. Marnane. New algorithm for LDPC decoding over GF(q). In IEE Irish Signals and Systems Conference 2005, pages 425--430. IEE, September 2005.

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