Richard Bresnan


Richard Bresnan

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Richard Bresnan graduated in 2004.

Masters Thesis Title: Novel Code Construction and Decoding Techniques for LDPC Codes

Abstract: The record breaking error correcting codes known as low-density parity-check (LDPC) codes are studied. Background research in coding theory, graph theory and LDPC codes is described before the main work.

simulated sum-product decoder is implemented in software in the probability and log domains. Finite precision decoders are also implemented, which approximate the performance of a hardware implementation.

Detailed and very accurate decoding results are obtained, by implementing the simulated decoding environment in parallel for use on a computer cluster. The decoding of graphical images is demonstrated. Numerically biased sum-product decoders are investigated and are found to have superior decoding performance to the standard sum-product algorithm.

A novel sleeping node LDPC decoder is presented, which works by predicting the state of transmitted bits before the standard iterative decoding process has completed. Empirical evidence suggests that the decoder is sub-optimal, but more efficient than standard sum-product decoding. Hardware implementation issues are investigated. Results of varia constructed LDPC codes and it is shown that the decoding performance of the quasicyclic codes is at least as good as the random constructions for short block lengthstions on this decoder are described and it is shown how power savings of 40% can be achieved, while suffering an acceptable performance loss. Several random LDPC code constructions are developed that aim to either search for or grow random LDPC codes with high girth averages. Results of different techniques are compared with standard LDPC codes in the literature. It is shown that short length random codes have a decoding performance that is superior to most literature codes and moderate length random codes have a decoding performance comparable to literature codes.

Quasicyclic LDPC code constructions are defined and investigated. Families of these codes are categorised. Rules are developed to ensure that these codes are free of cycles of length four. Hardware implementation benefits are discussed. Results of decoding simulations are compared with randomly.

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