Patrick Twomey

Name:

Patrick Twomey

Contact Details:

Position:

M.Eng.Sc

Category:

Research

Biography

Patrick Twomey graduated in 2004.

Masters Thesis Title: Video Test Bed of an FPGA-Based Low-Density Parity Check Coding System

Abstract: This thesis is concerned with the subject of coding theory and in particular, a type of error correction code called low-density parity check (LDPC) codes. The goal of this thesis is to develop a hardware implementation of a video-based communication system with an LDPC error correction coding scheme.

Firstly, background theory on coding theory is presented and this is developed upon to demonstrate how the powerful LDPC codes operate. The message-passing algorithm that LDPC decoders are based on is explained and the hardware implications of implementing this algorithm are discussed. A parallel architecture to realise this algorithm is developed and a particular FPGA-based decoder is implemented.

This parallel LDPC decoder is converted to a serial architecture and the two types of architectures are compared and contrasted. The advantages of a parallel architecture is that it has a high throughput but at a cost of a large area footprint, while, on the other hand, a serial architecture uses much less area than a parallel implementation of the same code but its achievable throughput is much less. However, the area saving is such that a serial architecture can implement a much larger code and/or better resolution than a parallel architecture that uses the same amount of area. This means that a serial architecture can have better BER performance than a parallel architecture that has the same area footprint.

The video technology required for such a system is investigated and the video input and output systems are developed. The design issues involved in their practical implementations and the details of their construction are presented. The communications channel for this error correction code transmission system is investigated, a practical system presented and its design issues discussed. The various sub-systems are integrated although a complete system is not realised. However, a working video-based communication system has been built and LDPC decoding architectures have been investigated in detail.

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