-- ================================================================================================
-- Hash Function Wrapper
-- ================================================================================================
-- Claude Shannon Institute for Discrete Mathematics, Coding, Cryptography and Information Security
-- Department of Electrical and Electronic Engineering
-- University College Cork
-- Cork
-- Ireland
-- http://www.ucc.ie/en/crypto/
-- http://shannoninstitute.ie/
--{neilh,brianb,markh,liam}@eleceng.ucc.ie
--
-- January 2010
-- ver 6a - 09/03/10
-- ================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

library work;
use work.wrapper_pkg.all;

-- entity declaration
entity wrapper is
	port (
		clk			: in  std_logic;
		rst			: in  std_logic;
		ack_in		: out std_logic;						-- data on input bus has been read
		dp_in		: in  std_logic;						-- data present on input bus
		lb_in		: in  std_logic;						-- data present on input bus is the last block
		data_in		: in  std_logic_vector(BWS-1 downto 0);	-- input bus
		ack_out		: in  std_logic;						-- data on output bus has been read
		dp_out		: out std_logic;						-- data present on output bus
		lb_out		: out std_logic;						-- data present on output bus is the last block
		data_out	: out std_logic_vector(BWS-1 downto 0)	-- output bus
	);
end wrapper;

-- ================================================================================================
architecture rtl of wrapper is
	
	-- ********************************************************************************************
	-- SHA-2	- 0			Fugue	- 5			Luffa		- 10
	-- BLAKE	- 1			Grostl	- 6			Shabal		- 11
	-- BMW		- 2			Hamsi	- 7			SHAvite-3	- 12
	-- Cubehash	- 3			JH		- 8			SIMD		- 13
	-- ECHO		- 4			Keccak	- 9			Skein		- 14
	-- ********************************************************************************************
	constant CTW	: natural	:= 64;		-- counter size
	constant DIG	: natural	:= 512;		-- digest size
	constant HFN	: natural	:= 7;		-- hash function number
	constant MES	: natural	:= 64;	-- message input size
	constant SAL	: natural	:= 0;		-- salt size
	-- ********************************************************************************************

	-- signal declaration
	signal ack_h_in, dp_h_in, lb_h_in	: std_logic; 
	signal ack_h_out, dp_h_out			: std_logic;
	signal ctr_en, ctr_cl				: std_logic;
	signal mes_in						: std_logic_vector(MES-1 downto 0);
	signal hash_out						: std_logic_vector(DIG-1 downto 0);
	signal sel_in						: std_logic_vector(2 downto 0);
	signal sel_out						: std_logic_vector(1 downto 0);
	
	-- hash function component declaration
	component hash
		generic (	CTW			: natural;
					DIG			: natural;
					HFN			: natural;
					MES			: natural;
					SAL			: natural);
		port (		clk			: in  std_logic;
					rst			: in  std_logic;
					ack_in		: out std_logic;
					dp_in		: in  std_logic;
					lb_in		: in  std_logic;
					data_in		: in  std_logic_vector(MES-1 downto 0);
					ack_out		: in  std_logic;
					dp_out		: out std_logic;
					data_out	: out std_logic_vector(DIG-1 downto 0));
	end component;
	
	-- controller component declaration
	component controller
		generic (	CTW			: natural;
					DIG			: natural;
					HFN			: natural;
					MES			: natural);
		port (		clk			: in  std_logic;
					rst			: in  std_logic;
					ack_in		: out std_logic;
					dp_in		: in  std_logic;
					lb_in		: in  std_logic;
					ack_out		: in  std_logic;
					dp_out		: out std_logic;
					lb_out		: out std_logic;
					ctr_en		: out std_logic;
					ctr_cl		: out std_logic;
					sel_in		: out std_logic_vector(2 downto 0);
					ack_h_in	: in  std_logic;
					dp_h_in		: out std_logic;
					lb_h_in		: out std_logic;
					ack_h_out	: out std_logic;
					dp_h_out	: in  std_logic;
					sel_out		: out std_logic_vector(1 downto 0));
	end component;
	
	-- output unit component declaration
	component output
		generic (	DIG		: natural);
		port (		clk		: in  std_logic;
					rst		: in  std_logic;
					sel_out	: in  std_logic_vector(1 downto 0);
					d_in	: in  std_logic_vector(DIG-1 downto 0);
					d_out	: out std_logic_vector(BWS-1 downto 0));
	end component;
	
	-- padding unit component declaration
	component padding
		generic (	CTW		: natural;
					DIG		: natural;
					HFN		: natural;
					MES		: natural);
		port (		clk		: in  std_logic;
					rst		: in  std_logic;
					ctr_en	: in  std_logic;
					ctr_cl	: in  std_logic;
					sel_in	: in  std_logic_vector(2 downto 0);
					d_in	: in  std_logic_vector(BWS-1 downto 0);
					d_out	: out std_logic_vector(DIG-1 downto 0));
	end component;

begin
	
	-- component assignment
	INST_hash : entity work.hash(rtl)
		generic map (CTW=>CTW, DIG=>DIG, HFN=>HFN, MES=>MES, SAL=>SAL)
		port map (clk=>clk, rst=>rst, ack_in=>ack_h_in, dp_in=>dp_h_in, lb_in=>lb_h_in, mes_in=>mes_in, ack_out=>ack_h_out, dp_out=>dp_h_out, hash_out=>hash_out);

	INST_controller : entity work.controller(behaviour)
		generic map (CTW=>CTW, DIG=>DIG, HFN=>HFN, MES=>MES)
		port map (clk=>clk, rst=>rst, ack_in=>ack_in, dp_in=>dp_in, lb_in=>lb_in, ack_out=>ack_out, dp_out=>dp_out, lb_out=>lb_out, ctr_en=>ctr_en, ctr_cl=>ctr_cl, sel_in=>sel_in, ack_h_in=>ack_h_in, dp_h_in=>dp_h_in, lb_h_in=>lb_h_in, ack_h_out=>ack_h_out, dp_h_out=>dp_h_out, sel_out=>sel_out);

	INST_output : entity work.output(logic)
		generic map (DIG=>DIG)
		port map (clk=>clk, rst=>rst, sel_out=>sel_out, d_in=>hash_out, d_out=>data_out);
		
	INST_padding : entity work.padding(logic)
		generic map (CTW=>CTW, DIG=>DIG, HFN=>HFN, MES=>MES)
		port map (clk=>clk, rst=>rst, ctr_en=>ctr_en, ctr_cl=>ctr_cl, sel_in=>sel_in, d_in=>data_in, d_out=>mes_in);
	
end rtl;