-- ================================================================================================
-- Hash Function Wrapper - Padding Unit
-- ================================================================================================
-- Claude Shannon Institute for Discrete Mathematics, Coding, Cryptography and Information Security
-- Department of Electrical and Electronic Engineering
-- University College Cork
-- Cork
-- Ireland
-- http://www.ucc.ie/en/crypto/
-- http://shannoninstitute.ie/
--{neilh,brianb,markh,liam}@eleceng.ucc.ie
--
-- January 2010
-- ver 1a - 25/01/10
--
-- generic
--	* CTW	: counter width
--	* DIG	: message digest
--	* HIG	: hash function
--	* MES	: message width
-- ================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

library work;
use work.wrapper_pkg.all;

-- entity declaration
entity padding is
	generic (
		CTW	: natural;									-- counter width
		DIG	: natural;									-- message digest
		HFN	: natural;									-- hash function
		MES	: natural									-- message width
	);
	port (
		clk		: in  std_logic;
		rst		: in  std_logic;
		ctr_en	: in  std_logic;						-- counter enable
		ctr_cl	: in  std_logic;						-- counter clear
		sel_in	: in  std_logic_vector(2 downto 0);		-- bus multiplexor select
		d_in	: in  std_logic_vector(BWS-1 downto 0);	-- data in
		d_out	: out std_logic_vector(MES-1 downto 0)	-- data out
	);
end padding;

-- ================================================================================================
architecture logic of padding is

	component pad_hamsi64
		generic (	CTW		: natural);
		port (		clk		: in  std_logic;
					rst		: in  std_logic;
					ctr_en	: in  std_logic;
					ctr_cl	: in  std_logic;
					sel_in	: in  std_logic_vector(2 downto 0);
					d_in	: in  std_logic_vector(BWS-1 downto 0);
					d_out	: out std_logic_vector((2*BWS)-1 downto 0));
	end component;

begin
	
	COND_pad_hamsi64 : if ((HFN=7) and ((DIG=384) or (DIG=512))) generate
		INST_pad_hamsi64 : entity work.pad_hamsi64(logic)
			generic map (CTW=>CTW)
			port map (clk=>clk, rst=>rst, ctr_en=>ctr_en, ctr_cl=>ctr_cl, sel_in=>sel_in, d_in=>d_in, d_out=>d_out);
	end generate;

end logic;