-- ================================================================================================
-- Hash Function Wrapper - Register Size of 2*W
-- ================================================================================================
-- Claude Shannon Institute for Discrete Mathematics, Coding, Cryptography and Information Security
-- Department of Electrical and Electronic Engineering
-- University College Cork
-- Cork
-- Ireland
-- http://www.ucc.ie/en/crypto/
-- http://shannoninstitute.ie/
--{neilh,brianb,markh,liam}@eleceng.ucc.ie
--
-- January 2010
-- ver 2a - 11/03/10
-- ================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

library work;
use work.wrapper_pkg.all;

-- entity declaration
entity pad_hamsi64 is
	generic (
		CTW		: natural									-- counter width
	);
	port (
		clk		: in  std_logic;
		rst		: in  std_logic;
		ctr_en	: in  std_logic;							-- counter enable
		ctr_cl	: in  std_logic;							-- counter clear
		sel_in	: in  std_logic_vector(2 downto 0);			-- bus multiplexor select
		d_in	: in  std_logic_vector(BWS-1 downto 0);		-- data in
		d_out	: out std_logic_vector((2*BWS)-1 downto 0)	-- data out
	);
end pad_hamsi64;

-- ================================================================================================
architecture logic of pad_hamsi64 is
	
	-- constant declaration
	constant S				: natural							:= log2c(BWS);

	constant ZERO			: std_logic_vector(BWS-2 downto 0)	:= (others=>'0');
	constant ZERO_S			: std_logic_vector(S-1 downto 0)	:= (others=>'0');
	
	-- signal declaration
	signal d_reg, d_next	: std_logic_vector((2*BWS)-1 downto 0);
	signal ctr				: std_logic_vector(CTW-S-1 downto 0);
		
begin
	
	-- output assignment
	d_out	<= d_reg;
	
	-- input counter
	process (clk, rst) 
	begin
		if (rst='1') then 
			ctr		<= (others=>'0');
		elsif (clk='1' and clk'event) then
			if (ctr_cl='1') then
				ctr	<= (others=>'0');
			elsif (ctr_en='1') then
				ctr	<= ctr + 1;
			end if;
		end if;
	end process;
	
	-- register assignment
	process(rst, clk)
	begin
		if (rst='1') then
			d_reg	<= (others=>'0');
		elsif (clk'event and clk='1') then
			d_reg	<= d_next;
		end if;
	end process;
	
	-- multiplexor assignment		
	d_next	<=	d_reg												when (sel_in="000") else
				d_reg(BWS-1 downto 0)	& d_in						when (sel_in="001") else
				d_reg(BWS-1 downto 0)	& '1'		& ZERO			when (sel_in="010") else
				'1' 					& ZERO		& '0'	& ZERO	when (sel_in="011") else
				ctr						& ZERO_S					when (sel_in="100") else
				'0'						& ZERO		& '0'	& ZERO;
				
end logic;