-- ================================================================================================
-- Hash Function Wrapper - Output Unit
-- ================================================================================================
-- Claude Shannon Institute for Discrete Mathematics, Coding, Cryptography and Information Security
-- Department of Electrical and Electronic Engineering
-- University College Cork
-- Cork
-- Ireland
-- http://www.ucc.ie/en/crypto/
-- http://shannoninstitute.ie/
--{neilh,brianb,markh,liam}@eleceng.ucc.ie
--
-- January 2010
-- ver 2d - 09/03/10
--
-- generic
--	* DIG	:	digest size required
-- ================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

library work;
use work.wrapper_pkg.all;

-- entity declaration
entity output is
	generic (
		DIG	: natural									-- digest size
	);
	port (
		clk		: in  std_logic;
		rst		: in  std_logic;
		sel_out	: in  std_logic_vector(1 downto 0);		-- multiplexor select for output register
		d_in	: in  std_logic_vector(DIG-1 downto 0);	-- data in
		d_out	: out std_logic_vector(BWS-1 downto 0)	-- data out
	);
end output;

-- ================================================================================================
architecture logic of output is
	
	-- constant declaration
	constant ZERO_W			: std_logic_vector(BWS-1 downto 0)	:= (others=>'0');
	
	-- signal declaration
	signal d_reg, d_next	: std_logic_vector(DIG-1 downto 0);
	
begin
	
	-- output assignment
	d_out	<= d_reg(DIG-1 downto DIG-BWS);
	
	-- register assignment
	process(clk, rst)
	begin
		if (rst='1') then
			d_reg <= (others=>'0');
		elsif (clk='1' and clk'event) then
			d_reg <= d_next;
		end if;
	end process;
	
	-- multiplexor assignment		
	d_next	<=	d_reg 								when (sel_out="00") else
				d_in								when (sel_out="01") else
				d_reg(DIG-BWS-1 downto 0) & ZERO_W	when (sel_out="10") else
				(others=>'0');
				
end logic;