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Book of Modules 2011/2012 |
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Microelectronic Engineering |
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UE2003 Microelectronic Physics
Credit Weighting: 5
Teaching Period(s): Teaching Period 1.
No. of Students: Min 20, Max 100.
Pre-requisite(s): None
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; Other (12hrs Laboratories).
Module Co-ordinator: Dr Paul Hurley, Tyndall Institute.
Lecturer(s): Staff, Tyndall Institute.
Module Objective: To teach the fundamentals of physics of electronic materials and devices.
Module Content: Physics of semiconductor materials (energy band theory, doping principles, diffusion and drift, recombination), Semiconductor substrate fabrication (phase diagrams, solid solubility), Metal-semiconductor contacts, pn junction physics, currents in pn junctions, physics of the MOS system, review of MOS materials and process technologies, MOS transistor physics, Bipolar Transistor physics
Learning Outcomes: On successful completion of this module, students should be able to:
· Summarise the main semiconductor properties, energy band, carrier concentration and transport, used for understanding electronic device characteristics
· Calculate substrate type, electron and hole concentrations, Fermi level and band diagram for a given doped semiconductor substrate.
· Describe the physics of p-n junction theory, as the building block of most semiconductor devices
· Discuss the physics of a metal-oxide-semiconductor (MOS) structure and its application to a Si-based MOS Field Effect Transistor (MOSFET)
· Discuss the physics of interaction between two closely coupled p-n junctions and application to the principle of operation of a basic bipolar transistor
· Perform simple experiments on and evaluate the performance of basic semiconductor transistors and photonic devices.
Assessment: Total Marks 100: End of Year Written Examination 80 marks (End of Year Written Examination); Continuous Assessment 20 marks (Lab Reports/Practicals).
Compulsory Elements: End of Year Written Examination; Continuous Assessment (lab reports/practicals).
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: 1 x 1½ hr(s) paper(s).
Requirements for Supplemental Examination: 1 x 1½ hr(s) paper(s) to be taken in Autumn. The mark for Continuous Assessment is carried forward.
UE3007 Digital Integrated Circuits
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 and 2.
No. of Students: Min 0, Max 100.
Pre-requisite(s): -
Co-requisite(s): -
Teaching Methods: 24 x 1hr(s) Lectures; 12 x 1hr(s) Practicals.
Module Co-ordinator: Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Lecturer(s): Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Module Objective: To impart an understanding of the operation and design of the main building blocks of digital circuits.
Module Content: MOS transistors, SPICE parameters; static and switching characteristics, parasitic elements, noise margins, propagation delay; power/energy consumption and speed limit of CMOS processes, layout of basic CMOS digital circuits.
Learning Outcomes: On successful completion of this module, students should be able to:
· Characterise the MOS transistors and CMOS logic through various metrics;
· Design a multi-transistor CMOS circuit to meet a target set of specifications, simulate its performance using the SPICE circuit simulator;
· Identify parasitic elements and analyse propagation behaviour for given process technology SPICE parameters;
· Calculate and analyse noise margins of CMOS circuits;
· Calculate and analyze propagation delay and power/energy consumption of CMOS circuits;
· Design layouts for basic digital integrated circuits;
· Get an insight into the post-CMOS digital ICs.
Assessment: Total Marks 100: End of Year Written Examination 80 marks; Continuous Assessment 20 marks (Lab Reports/Practicals).
Compulsory Elements: End of Year Written Examination; Continuous Assessment.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 5% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 10% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: 1 x 1½ hr(s) paper(s) to be taken in Spring.
Requirements for Supplemental Examination: 1 x 1½ hr(s) paper(s) to be taken in Autumn. The mark for Continuous Assessment is carried forward.
UE3008 Analogue Integrated Circuits
(Last updated 07/11/2011)
Credit Weighting: 5
Teaching Period(s): Teaching Period 1.
No. of Students: Max 100.
Pre-requisite(s): EE2007 , UE2003
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; 12 x 1hr(s) Practicals.
Module Co-ordinator: Prof Michael Peter Kennedy, Department of Microelectronic Engineering.
Lecturer(s): Prof Michael Peter Kennedy, Department of Microelectronic Engineering.
Module Objective: To impart an understanding of the operation and design of the main building blocks of analogue integrated circuits.
Module Content: Transistor models, single transitor stages, current mirror; invertors; differential gain stages; 2-stage CMOS op amps;frequency response.
Learning Outcomes: On successful completion of this module, students should be able to:
· Present models of CMOS and bipolar junction transistors, write analytical expressions for the input and output driving point characteristics of bipolar and MOS transistors and write analytical expressions for the resistive and capacitive components of the small-signal modules.
· Analyse the DC performance of current mirrors, single stage amplifiers, differential gain stages, and two-stage op amps, analyse the frequency response of one- and two-stage amplifiers.
· Build a differential amplifier, measure key performance specifications and explain the differences between these and those predicted by a simplified model.
· Design a multi-transistor CMOS circuit to meet a target set of specifications, simulate its performance using the SPICE circuit simulator and explain the differences between the simulated performance and that predicted by using simplified transistor models.
Assessment: Total Marks 100: End of Year Written Examination 80 marks; Continuous Assessment 20 marks (Lab Reports/Practicals).
Compulsory Elements: End of Year Written Examination; Continuous Assessment. Lab Reports/Practicals.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 5% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 10% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: 1 x 1½ hr(s) paper(s) to be taken in Spring.
Requirements for Supplemental Examination: 1 x 1½ hr(s) paper(s) to be taken in Autumn. The mark for Continuous Assessment is carried forward.
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 and 2.
No. of Students: Max 100.
Pre-requisite(s): UE3007
Co-requisite(s): None
Teaching Methods: 48 x 1hr(s) Lectures.
Module Co-ordinator: Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Lecturer(s): Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Module Objective: To study design techniques and the design flow for digital ICs and circuits.
Module Content: Introduction to CMOS digital logic. CMOS architectures for combinational and sequential circuits, memory design. low power design techniques for digital ICs, digital IC design flow (from high level synthesis to layout).
Learning Outcomes: On successful completion of this module, students should be able to:
· Synthesize and analyse CMOS logic circuits of different design architectures in terms of speed, area and design effort;
· Optimize a digital circuit for area, timing or power;
· Obtain an appreciation of the role of interconnect in the context of digital integrated circuits and systems;
· Get an insight into post-CMOS digital IC's;
· Describe the principals of an Integrated Circuit design flow, including simulation at various levels of abstraction, high level synthesis, logic synthesis and optimization, partitioning/placement/routing, floor planning and layout.
Assessment: Total Marks 100: End of Year Written Examination 100 marks.
Compulsory Elements: End of Year Written Examination.
Penalties (for late submission of Course/Project Work etc.): None.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: 1 x 3 hr(s) paper(s).
Requirements for Supplemental Examination: 1 x 3 hr(s) paper(s) to be taken in Autumn.
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 and 2.
No. of Students: Max 130.
Pre-requisite(s): UE3003
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; Other (24hrs practical Assignments).
Module Co-ordinator: Prof Michael Peter Kennedy, Department of Microelectronic Engineering.
Lecturer(s): Staff, Department of Electrical and Electronic Engineering.
Module Objective: To study design techniques for analogue ICs.
Module Content: Single and multiple stage transistor amplifiers. Operational amplifiers. Feedback amplifiers, two-port formulation, source, load, and feedback network loading. Frequency response of cascaded amplifiers, gain-bandwidth exchange, compensations, dominant pole techniques, root locus. Supply and temperature-independent biasing and references. Selected applications of analogue circuits such as analogue-to-digital converters, switched capacitor filters, and comparators.
Learning Outcomes: On successful completion of this module, students should be able to:
· Derive the level1 model for MOSFET operation and understand its limitations in sub-micron CMOS processes.
· Analyse DC biasing, construct small-signal models, derive expressions for and calculate the gain of single-stage amplifiers, differential amplifiers and opamp circuits.
· Analyse dc biasing, accuracy and compliance of simple and high-performance current mirrors.
· Use principles of two-port analysis to derive transconductance, input and output resistance of circuits and apply these principles in determining the gain by observation of relatively complex opamp circuits.
· Analyse the high-frequency response of single-stage amplifiers, differential amplifiers and opamp circuits and analyse the stability of opamp circuits when used in negative feedback configurations and apply frequency compensation techniques to ensure stability.
· Perform noise analysis of single-stage amplifiers and differential amplifiers and calculate the signal-to-noise ratios of these circuits.
· Understand the concept of transistor mismatch and use basic MOS mismatch model and small-signal techniques to predict the mismatch of current mirrors and calculate the input-referred offset of amplifiers.
· Set-up the basic features of Cadence design framework, use the schematic entry tool, create hierarchical designs and perform DC, AC and transient simulations of circuits studied in the course using the Spectre simulator.
· Assess the stability of negative feedback opamp circuits in Spectre by the method of opening the loop, and the Cadence stability analysis tool, and compensate to ensure stability.
Assessment: Total Marks 100: End of Year Written Examination 70 marks (End of year written examination); Continuous Assessment 30 marks (Lab Reports/Practicals).
Compulsory Elements: End of Year Written Examination; Lab Reports/Practicals.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: 1 x 1½ hr(s) paper(s).
Requirements for Supplemental Examination: 1 x 1½ hr(s) paper(s) to be taken in Autumn. The mark for Continuous Assessment is carried forward.
UE4008 Processing of Integrated Circuits
Credit Weighting: 5
Teaching Period(s): Teaching Period 1.
No. of Students: Max 100.
Pre-requisite(s): UE3003
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; 24 x 1hr(s) Practicals.
Module Co-ordinator: Mr Brendan O'Neill, Tyndall Institute.
Lecturer(s): Mr Brendan O'Neill, Tyndall Institute.
Module Objective: To describe the IC fabrication process and how process issues affect the finished device characteristics
Module Content: Introduction to the IC manufacturing industry, thermal oxidation of silicon, photolithography, etch processes, diffusion and implantation, CVD processes, metallisation, process integration, technology roadmaps, introduction to process simulation and device probing.
Learning Outcomes: On successful completion of this module, students should be able to:
· Identify sources for current information and future trends in IC manufacturing technology
· Describe in essay style what physically happens at each technology stage of the process
· Use clear diagrams to graphically illustrate how the equipment used operates
· Use clear graphs to illustrate the physics of the processes described
· Relate the equations that govern the physics of the processes to the textual descriptions
· Calculate using equations relating to each technology key parameters for those processes
· Describe how each of the sub-technologies or processes combine to make up the full IC manufacturing process
· Illustrate how problems or changes in the sub-technologies affect the measured parameters of the individual devices
· Relate with reference to the device equations how changes in the processes affect the device parameters.
Assessment: Total Marks 100: End of Year Written Examination 70 marks (End of year written exam); Continuous Assessment 30 marks (Lab Report/Practicals).
Compulsory Elements: End of Year Written Examination; Lab Report/Practicals.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: 1 x 1½ hr(s) paper(s).
Requirements for Supplemental Examination: 1 x 1½ hr(s) paper(s) to be taken in Autumn. The mark for Continuous Assessment is carried forward.
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 or 2.
No. of Students: Min 10.
Pre-requisite(s): None
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; Practicals (12hrs Laboratories).
Module Co-ordinator: Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Lecturer(s): Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Module Objective: To teach HDL languages used in the IC design flow
Module Content: Overview of state of the art IC design flows. The VHDL language: data types and operations; sequential statements, concurrent statements; synthesis subset. The Verilog language: data types and operations; abstractions levels in Verilog; modules, ports, basic blocks; timing control; Verilog subset for logic synthesis
Learning Outcomes: On successful completion of this module, students should be able to:
· State the importance of using HDL languages as part of a digital IC design flow;
· Define synthesis, optimization, and simulation of digital circuits;
· Use the HDL languages to capture the concurrency and process communication specific to hardware systems;
· Distinguish between synthesizable and simulation statements in both VHDL and Verilog;
· Use VHDL and Verilog to describe sequential and combinational circuits;
· Use VHDL and Verilog to efficiently design testbenches;
· Use HDL in the context of design for re-use.
Assessment: Total Marks 100: End of Year Written Examination 70 marks (End of Year Written Examination); Continuous Assessment 30 marks (Lab Report/Practicals).
Compulsory Elements: End of Year Written Examination; Continuous Assessment (Lab Report/Practicals).
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: No End of Year Written Examination.
Requirements for Supplemental Examination: Marks in passed element(s) of Continuous Assessment are carried forward, Failed element(s) of Continuous Assessment must be repeated (1 x 1½hr written examination to be organised by the Department).
Credit Weighting: 5
Teaching Period(s): Teaching Period 2.
No. of Students: Min 5.
Pre-requisite(s): none
Co-requisite(s): none
Teaching Methods: 16 x 90min(s) Lectures.
Module Co-ordinator: Dr Georgios Fagas, Tyndall Institute.
Lecturer(s): Dr Georgios Fagas, Tyndall Institute; Dr Aidan Quinn, Tyndall Institute; Prof Jean-Pierre Colinge, Tyndall Institute.
Module Objective: To teach advanced topics in nanoelectronics
Module Content: From microelectronics to nanoelectronics, challenges and objectives and overview/examples of measured effects;
Primary quantum mechanics;
Top-down nanofabrication:CMOS scaling, multi-gate transistors, junctionless transistors;
Electronic structure of confined systems: appplication to nanoscale structures (e.g. Si nanowires, graphene, nanotubes);
Bottom-up synthesis, directed assembly and electrical contacting of nanoscale building blocks:nanowires, nanotubes, graphene, nanocrystals;
Quantum transport: elementary theory and effects (e.g. conductance quantisation and fluctuations, coherent and single-electron tunnelling);
Principles of nanoelectronic devices (e.g. multigate FET, Junctionless FET, SET);
Device operation and performance (benchmarking bottom-up vs top-down)
Learning Outcomes: On successful completion of this module, students should be able to:
· Illustrate key electronic structure and quantum transport properties of low-dimensional systems using analytical methods and basic numerical computations (e.g. in MATLAB).
· Analyse the operating principles of nanoscale electronic devices and interpret measured device data, with particular reference to:
novel non-planar silicon devices (multi-gate transistors, junctionless transistors),
nanowire devices,
graphene devices,
molecular electronic devices.
· Compare and contrast candidate device performance based on fundamental limitations and their (ultimate)potential for high-volume manufacturing.
· Recognise the near- and medium-term scaling challenges associated with continued miniaturisation in conventional "top-down" semiconductor technology at and below the 22nm node.
· Summarise the benefits and challenges associated with bottom-up fabrication of nanostructures for future applications in electronics.
Assessment: Total Marks 100: Continuous Assessment 100 marks (Lab report/Practical 30 marks, In-class exam 70 marks).
Compulsory Elements: Continuous Assessment.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: No End of Year Written Examination.
Requirements for Supplemental Examination: Marks in passed element(s) of Continuous Assessment are carried forward, Failed element(s) of Continuous Assessment must be repeated (90 minute in class exam (corresonding to Lab Report/Practical and In class exam)).
UE6006 Advanced Analogue IC Design
(Last updated 03/11/2011)
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 or 2.
No. of Students: Min 8.
Pre-requisite(s): None
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; 12 x 1hr(s) Practicals.
Module Co-ordinator: Dr Domenico Zito, Department of Microelectronic Engineering.
Lecturer(s): Dr Domenico Zito, Department of Microelectronic Engineering.
Module Objective: Principles of advanced analog IC design.
Module Content: Design of precision analogue blocks in CMOS and BiCMOS technologies; Review of VLSI Analog design constraints; Wide-band amplifier design; Operational amplifier design; Voltage and Current Reference Design; Gm/C filters; Sample and Hold Circuits; Switched Capacitor filters
Learning Outcomes: On successful completion of this module, students should be able to:
· Perform noise analysis on circuits containing resistors, inductors, capacitors, diodes, transistors and operational amplifiers;
· Analyse sample-and-hold circuits, taking account of non-ideal effects;
· Design biploar and MOS circuits for bandgap references;
· Explain the spectral transformations in a typical signal processing chain resulting from anti-alias filtering, sampling, analog-to-digital conversion up- and down-sampling, digital-to-analog conversion, and reconstruction filtering;
· Use the bilinear transform to design first- and second-order discrete -time filters;
· Model and analyse switched-capacitor circuits in the time and z-domains.
Assessment: Total Marks 100: Continuous Assessment 100 marks (including In-Class Written Examination 70 marks).
Compulsory Elements: Continuous Assessment.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: No End of Year Written Examination.
Requirements for Supplemental Examination: Marks in passed element(s) of Continuous Assessment are carried forward, Failed element(s) of Continuous Assessment must be repeated (1 x 1½hr written examination to be organised by the Department).
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 and 2.
No. of Students: Min 20.
Pre-requisite(s): UE3002
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; Other (24hrs Practical Assignments).
Module Co-ordinator: Dr Aidan Quinn, Tyndall Institute.
Lecturer(s): Staff, Tyndall Institute.
Module Objective: To describe the principles and fundamental building blocks of key nanoscale devices and technologies
Module Content: Nanoelectronics: Introduction to low dimensional physics; transport in low dimensional systems; heterostructure devices; quantum device operation. Nanophotonics: Band structure engineering for photonic devices; photonic device fabrication technologies; survey of key devices: LEDs, RCLEDs, VCSELs, microdisks, quantum dot devices, single photon devices. Emerging technologies: Mesoscopic physics: wave function coherence, tunnelling; devices based on ballistic transport, single charge tunnelling, resonant tunnelling; fabrication and assembly at the nanoscale; nanoscale visualisation and characterisation; molecular scale electronic devices.
Learning Outcomes: On successful completion of this module, students should be able to:
· Describe the lithography, materials and design challenges associated with top-down scaling for CMOS technology at and below the 45nm node;
· Summarise the near- and medium- term scaling challenges associated wtih continued miniaturisation in CMOS technology;
· Identify the relevant length and energy scales associated with novel or enhanced electronic and/or optical properties in nanoscale structures e.g single electron tunneling and quantum confinement;
· Calculate order-of-magnitude estimates for the electronic and/or optical characteristics of nanostructures, e.g. barrier tunnel currents or energy levels in quantum dots;
· Analyse the operating principles of nanoscale electronic and photonic devices and describe the advantages and disadvantages of such devices;
· Identify the potential performance enhancement associated with nanostructure-based devices and summarise the challenges associated with developing manufacturable technologies;
· Summarise the benefits and challenges associated with bottom-up fabrication of nanostructures for applications in electronics and photonics.
Assessment: Total Marks 100: End of Year Written Examination 70 marks; Continuous Assessment 30 marks.
Compulsory Elements: End of Year Written Examination; Continuous Assessment.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40% average with not less than 30% in the written examination or Continuous Assessment. For students who do not satisfy this requirement, the lower of the two marks, calculated as a percentage of the total mark for the module, will be returned.
End of Year Written Examination Profile: 1 x 1½ hr(s) paper(s).
Requirements for Supplemental Examination: 1 x 1½ hr(s) paper(s) to be taken in Autumn. The mark for Continuous Assessment is carried forward.
UE6008 Microsystems Technology and Applications
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 and 2.
No. of Students: Max 50.
Pre-requisite(s): UE3002
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; Other (24hrs Practical Assignment).
Module Co-ordinator: Dr Cian O Mathuna, Tyndall Institute.
Lecturer(s): Staff, Tyndall Institute.
Module Objective: To teach the basic principles of microsystems and illustrate these principles with relevant applications
Module Content: Introduction to microsystems technology, concepts, materials, application areas; materials and properties (Si, III-V, polymers, glass); design, modelling, fabrication; devices, sensors and actuators, passive, active and MEMs, interface electronics; integration, packing, assembly, optics and microfluidics; test and reliability; applications: telecoms (DWDM, RF), intelligent environment, biological, chemical, medical.
Learning Outcomes: On successful completion of this module, students should be able to:
· Understand the concept of microsystems and their relationship to mainstream microelectronics.
· Appreciate the applications of microsystems across a broad landscape encompassing communications, energy, health and the environment.
· Describe the common processing techniques used in MEMS manufacturing and how these processing techniques are used to fabricate MEMS devices.
· Outline the main challenges encountered in microsystems design and evaluate different types of modelling tools used for microsystem design.
· Understand the complexity of microsystems packaging, identifying the diversity of challenges that microsystems packaging brings to the system designer.
· Show that packaging can be used as a low cost and efficient way to create a systems level design rather than building it all in one chip and comprehend the advantages offered by three dimensional integration technologies.
· Identify the main failure mechanisms encountered in microsystems and how to improve their design to reduce the probability of failure occurring.
· Select the optimal biosensor device(s) based on an understanding of the requirements of any specific biological application.
· Describe the most commonly used biosensors with respect to their mode of operation and identify their merits and limitations.
Assessment: Total Marks 100: End of Year Written Examination 70 marks (End of Year Written Examination); Continuous Assessment 30 marks (In Class Presentations).
Compulsory Elements: End of Year Written Examination; Continuous Assessment (In Class Presentations).
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: 1 x 1½ hr(s) paper(s).
Requirements for Supplemental Examination: 1 x 1½ hr(s) paper(s) to be taken in Autumn. The mark for Continuous Assessment is carried forward.
UE6009 Data Converter IC Design
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 or 2.
No. of Students: Max 50.
Pre-requisite(s): None
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; Practicals (12hrs Laboratories).
Module Co-ordinator: Prof Michael Peter Kennedy, Department of Microelectronic Engineering.
Lecturer(s): Staff, Department of Electrical and Electronic Engineering.
Module Objective: Principles of data converter IC design
Module Content: Design of precision data converter (ADC and DAC) blocks in CMOS and BiCMOS technologies; Successive Approximation; Flash converters; Pipeline and folded pipeline converters; Sigma Delta low pass data converters.
Learning Outcomes: On successful completion of this module, students should be able to:
· Design and analyse single and dual string digital to analog converters (DACS)
· Design and analyse R2R and segmented R2R DACS
· Design and analyse current source DACS
· Analyse the frequency response of ideal DACS
· Design and analyse dual slope analog to digital converters (ADCS)
· Design and analyse SAR ADCS
· Design and analyse flash ADCS
· Design and analyse sigma delta modulators with particular detail on noise shaping
· Design and analyse sinc filters for sigma delta DACs and ADCs.
Assessment: Total Marks 100: Continuous Assessment 100 marks (In Class Test).
Compulsory Elements: Continuous Assessment (In Class Test).
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: No End of Year Written Examination.
Requirements for Supplemental Examination: 1 x 3 hr(s) paper(s) to be taken in Autumn. The mark for Continuous Assessment is carried forward.
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 and 2.
No. of Students: Max 50.
Pre-requisite(s): EE1003, UE3005
Co-requisite(s): None
Teaching Methods: 24hr(s) Lectures; 24hr(s) Other (Practical Assignments).
Module Co-ordinator: Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Lecturer(s): Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Module Objective: Principles of Microelectronic System Design
Module Content: Embedded systems design flow, hardware-software co-design, system modelling, performance estimation, hardware-software partitioning, co-simulation, co-synthesis; interface design. Systems on a Chip(SoC) and Field Programmable systems on chip(FPSoC), IP cores, SoC verification and test.
Learning Outcomes: On successful completion of this module, students should be able to:
· Explain the importance and challenges of designing embedded systems;
· Describe an embedded system design flow from specification to physical realization;
· Estimate the cost and the performance of a hardware-software system(timing, power consumption);
· Describe issues related to communication between processes, interface design;
· Define IP cores and challenges in automating the design process for SoC;
· Describe SoC verification and test.
Assessment: Total Marks 100: End of Year Written Examination 70 marks (End of Year Written Examination); Continuous Assessment 30 marks (Lab Reports/Practicals).
Compulsory Elements: End of Year Written Examination; Lab Reports/Practicals.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: 1 x 1½ hr(s) paper(s).
Requirements for Supplemental Examination: 1 x 1½ hr(s) paper(s) to be taken in Autumn. The mark for Continuous Assessment is carried forward.
UE6011 Frequency Synthesizer Design
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 or 2.
No. of Students: Min 10.
Pre-requisite(s): None
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; Other (12hrs Laboratories).
Module Co-ordinator: Prof Michael Peter Kennedy, Department of Microelectronic Engineering.
Lecturer(s): Staff, Department of Microelectronic Engineering.
Module Objective: To teach the basic principles of frequency synthesizer design.
Module Content: PLL theory and stability analysis; single loop PLL: analysis and design, high frequency prescalers and dual modulus prescalers, phase detectors, charge pumps, loop filters, VCOs, sideband noise spurs and harmonics; fractional-N synthesizers; multiple loop PLLs; direct digital synthesis
Learning Outcomes:
Assessment: Total Marks 100: Continuous Assessment 100 marks (including In-Class Written Examination 70 marks).
Compulsory Elements: Continuous Assessment.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: No End of Year Written Examination.
Requirements for Supplemental Examination: Marks in passed element(s) of Continuous Assessment are carried forward, Failed element(s) of Continuous Assessment must be repeated (1 x 1½hr written examination to be organised by the Department).
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 and 2.
No. of Students: Min 10.
Pre-requisite(s): EE1003
Co-requisite(s): None
Teaching Methods: 24hr(s) Lectures; 24hr(s) Other (Practical Assignments).
Module Co-ordinator: Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Lecturer(s): Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Module Objective: To teach the fundamentals of testing and design for test for microelectronic integrated circuits
Module Content: Testing and verification, faults in digital circuits; fault modeling and simulation, test vector generation, cost of testing, design for test, scan path architecture, boundary scan standard, built in self test methodology, memory testing
Learning Outcomes: On successful completion of this module, students should be able to:
· Define testing and verification;
· Define types of faults in a digital circuit and describe the most used fault models;
· Define and estimate the cost of testing; define fault coverage, fault dictionary, signature.
· Efficiently generate test vectors for a given combinational and sequential circuit;
· Use Scan-Path, Boundary Scan, Built-In-Self-Test(BIST), Built-In-Logic-Block-Observer(BILBO) architectures for a digital IC design;
· Define memory testing;
· Use methods to reduce the cost of testing for digital circuits.
Assessment: Total Marks 100: End of Year Written Examination 70 marks (End of Year Written Examination); Continuous Assessment 30 marks (Continuous Assessment (Lab Report/Practicals)).
Compulsory Elements: End of Year Written Examination; Continuous Assessment (Lab Report/Practicals).
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: 1 x 1½ hr(s) paper(s).
Requirements for Supplemental Examination: 1 x 1½ hr(s) paper(s) to be taken in Autumn. The mark for Continuous Assessment is carried forward.
UE6015 Advanced Radio-Frequency IC Design
Credit Weighting: 5
Teaching Period(s): Teaching Period 2.
No. of Students: Min 8.
Pre-requisite(s): None
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; 12 x 1hr(s) Practicals.
Module Co-ordinator: Dr Domenico Zito, Department of Microelectronic Engineering.
Lecturer(s): Dr Domenico Zito, Department of Microelectronic Engineering.
Module Objective: Principles of advanced RFIC Design in nano-scale silicon technology.
Module Content: Design of analog radiofrequency tranceivers in CMOS and BiCMOS technologies for emerging wireless applications.
Emerging wireless applications; transceiver architectures; systems and circuits design challenges; system and circuit specifications; design constraints and technology limitations; advanced circuit topologies and state-of-the-art design techniques for the main building blocks (Low Noise Amplifier, Voltage Controlled Oscillators, Mixers and Power Amplifiers);
latest advances in system-on-chip implementation.
Learning Outcomes: On successful completion of this module, students should be able to:
· Understanding the main challenges at system and circuit levels for implementation of radiofrequency tranceivers and their building blocks in nano-scale silicon technology.
· Design the building blocks of modern radiofrequency transceivers for emerging wireless applications by means of advanced circuit topologies and state-of-the-art design techniques.
· Use commercial advanced CAD tools for microelectronic RFIC design.
· Familiarize with the emerging wireless applications (data communication and contactless sensing) and the latest advances in the state of the art for the system-on-chip implementation of radiofrequency transceivers in the microwave and milimeter-wave frequency range.
Assessment: Total Marks 100: Continuous Assessment 100 marks (including in-class written examination, 70 marks).
Compulsory Elements: Continuous Assessment.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: No End of Year Written Examination.
Requirements for Supplemental Examination: Marks in passed element(s) of Continuous Assessment are carried forward, Failed element(s) of Continuous Assessment must be repeated (1 x 1.5 hr written examination to be organised by the Department).
Credit Weighting: 10
Teaching Period(s): Teaching Periods 1 and 2.
No. of Students: Max 50.
Pre-requisite(s): None
Co-requisite(s): None
Teaching Methods: Other (Report Work).
Module Co-ordinator: Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Lecturer(s): Staff, Department of Microelectronic Engineering.
Module Objective: To provide students with the opportunity to demonstrate their aptitude for research in microelectronic design.
Module Content: Topic chosen in consultation with Supervisor.
Learning Outcomes: On successful completion of this module, students should be able to:
· Disseminate/communicate their work through seminar presentations, oral examinations in the presence of an extern.
· Write research reports.
· Plan and develop milestones.
· Demonstrate their aptitude for research in microelectronic design.
Assessment: Total Marks 200: Continuous Assessment 200 marks (First Interim Report 100 marks; Second Interim Report 100 marks).
Compulsory Elements: Continuous Assessment.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: No End of Year Written Examination.
Requirements for Supplemental Examination: No Supplemental Examination.
Credit Weighting: 30
Teaching Period(s): Teaching Periods 1 and 2. (July, August, September).
No. of Students: Max 50.
Pre-requisite(s): UE5019
Co-requisite(s): None
Teaching Methods: Other (Project Work).
Module Co-ordinator: Dr Emanuel Popovici, Department of Electrical and Electronic Engineering.
Lecturer(s): Staff, Department of Microelectronic Engineering.
Module Objective: To provide students with the opportunity to apply their theoretical knowledge to a substantial microelectronic design problem requiring analytical and/or design and/or experimental effort.
Module Content: Topic chosen in consultation with supervisor.
Learning Outcomes: On successful completion of this module, students should be able to:
· Write a minor thesis.
· Plan and develop milestones.
· Research and implement within a chosen theme.
· Pursue project work in a research environment.
Assessment: Total Marks 600: Continuous Assessment 600 marks (Research Project).
Compulsory Elements: Research Project (Dissertaion: 600 marks).
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 10% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 20% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 50%.
End of Year Written Examination Profile: No End of Year Written Examination.
Requirements for Supplemental Examination: No Supplemental Examination.
UE6022 Packaging and Reliability
Credit Weighting: 5
Teaching Period(s): Teaching Periods 1 or 2.
No. of Students: Min 0.
Pre-requisite(s): None
Co-requisite(s): None
Teaching Methods: 24 x 1hr(s) Lectures; 12 x 1hr(s) Practicals (Labs).
Module Co-ordinator: Ms Orla Slattery, Tyndall Institute.
Lecturer(s): Dr Cian O Mathuna, Tyndall Institute; Ms Orla Slattery, Tyndall Institute; Mr Finbarr Waldron, Tyndall Institute.
Module Objective: To introduce the idea of microelectornics packaging and its critical impact on semiconducter device and circuit operation, performance and reliability. To provide an overview of the evolution and importance of reliability measurement and prediction in microelectronics.
Module Content: Introduction to Microelectronics packaging - Why Study Packaging, Processing from wafer to package; Emerging and future trends in microelectronics and MEMS packaging, including chip and wafer scale packaging; Thermal Characterisation of IC Packaging Technologies; Thermo-mechanical Characterisaton of IC Packaging Technologies; Reliability failure mechanisms; Reliability prediction theory, reliability measurements; Case studies.
Learning Outcomes: On successful completion of this module, students should be able to:
· Describe packaging processes;
· Discuss the evolution of packaging types;
· Identify packaging solutions for a range of application areas;
· Interpret emerging and future trends in packaging;
· Calculate electrical, thermal and thermomechanical performance;
· Evaluate the parameters affecting performance and identify how these parameters influence each other;
· Quantitatively analyse yield and reliability data;
· Discuss IC and component level failures and reliability concerns;
· Identify techniques for reliability evaluation and failure analysis.
Assessment: Total Marks 100: End of Year Written Examination 70 marks (End of Year Written Examination); Continuous Assessment 30 marks (Essay).
Compulsory Elements: End of Year Written Examination; Essay.
Penalties (for late submission of Course/Project Work etc.): Where work is submitted up to and including 7 days late, 5% of the total marks available shall be deducted from the mark achieved. Where work is submitted up to and including 14 days late, 10% of the total marks available shall be deducted from the mark achieved. Work submitted 15 days late or more shall be assigned a mark of zero.
Pass Standard and any Special Requirements for Passing Module: 40%.
End of Year Written Examination Profile: No End of Year Written Examination.
Requirements for Supplemental Examination: to be taken in Autumn. The mark for Continuous Assessment is carried forward, Marks in passed element(s) of Continuous Assessment are carried forward, Failed element(s) of Continuous Assessment must be repeated (1 x 1.5 hr in class Examination).
